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High-Performance 8-Bit Microcontrollers
Z8 Encore! XP(R) 4K Series
Product Specification
PS022815-0206
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. (c)2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Revision History
Each instance in the following table reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.
Revision History of this Document Revision Level
Date
Description Minor corrections made throughout document. Major changes include adding Timer caution note in the Timer chapter and Flash controller caution note in the Flash Memory chapter. In the Ordering chapter, corrected NVDS size typo. Added three new CPU instructions. Added 20-pin SOIC package drawing in Packaging chapter. Changed WDT oscillator frequency to 10 KHz in the Oscillator Control chapter. Clarified NVDS read/write operations in the NVDS Code Interface section. Minor corrections to Low-Power Modes, General Purpose I/O, Analog to 31,39, Digital Converter, Comparator, Flash Option Bits, Internal Precision 118,119,1 Oscillator, and Electrical Characteristics Chapters. 20,143,14 5,146,177, 202,203 Added 8-Pin Development Kit and USB Smart Cable Accessory Kit ordering information. Added clarifying information for using the UART Baud Rate Generator as a simplified timer. Removed 2.2VREF in Table 129. Changed VBO to LVD in Interrupt Controller. Changed PA5 T1OUT to T1OUT and added clarification of Ports A-C for 8-pin and 20/28 pin devices in Tables 21, 26 and 27 in the GPIO. Changed TPOR and TSMR typical values in Table 125, and Endurance minimum value in Table 126 in Electrical Characteristics. Removed 2.2V reference in Electrical Characteristics and Analog-to-Digital Converter chapters. Added clarifying text when writing to the Flash Control Register in Flash Memory chapter. Added Lead-Free Packaging order information 227 99, 129,39,50, 51,56,58, 59,61,43, 46,203, 204,206, 121,123, 126-140, 222-228
November 07 2004
December 08 2004
January 2005
09
May 2005 10
June 2005 11
Inserted missing temperature sensor chapter. Updated Figure1 to include 3, 5, 152, Transimpedance Amplifier. Added Transimpedance Amplifer to Feature 223, 227 Description. Removed reference to VBO enable. Updated Table 124 format. Changed Temperature Sensor column in ordering information pages.
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Revision History of this Document Revision Level 12
Date October 2005
Description Added references to optional low-power operational amplifier and 1-6, 8-12, removed references to transimpedance amplifier. Numerous other small 14-15, 17. corrections throughout the book. 19, 21-22, 24-27, 2931, 32-40, 44, 46, 48, 57-59, 62, 67-69, 7273, 75-76, 78, 81-89, 99-100, 102, 104105, 112125, 129140, 142144, 146151, 172177, 182, 204-223, 231, 237244 Reverted back to version 11, removing changes in version 12. Updated Flash Option Bits chapter. Restored version 12 changes and rectified elements to incorporate version 11 updates. 142-154 8, 84, 87, 88, 113, 124, 126, 148-161, 216, 218, 220, 221
November 13 2005 December 14 2005
February 2006
15
Updated for 8-pin QFN/MLF-S in Table 2, Figure 2, and Packaging 7, 8, 89 section. Updated UART features.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 2 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset, STOP Mode Recovery and Low Voltage Detection . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . STOP Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . STOP Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Debug Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 22 22 23 24 24 25 25 25 26 26 27 27 27 29 29 29 30 30 30 32 32 32 33 33 34 34 34 35 35
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External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-D Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-D Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-D Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-D Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . Port A-C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-D Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Level High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Timer 0-1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . Timer 0-1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . Timer 0-1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reload Upper, High and Low Byte Registers . . . . . . . . .
76 76 77 78 83 83 83 84 84 85 86 86 86 87
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . 91 Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . 92 Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . 94 Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . 103 UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 106 Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Trigger Point Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Compensation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Buffer Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Operational Amplifier (LPO) . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control/Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC High Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Low Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .
109 109 110 111 112 113 113 113 114 114 115 115 116 118 118 119 120 122 123 124 124 126 127 127 128 128 130 130 130 131
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Temperature Sensor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 136 137 138
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Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . Flash Code Protection Against Accidental Program and Erasure . . . . . . . Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Flash Information Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trim Bit Address 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZiLOG Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Randomized Lot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140 140 140 142 142 142 143 143 144 144 145 145 146 147 148 148 148 148 149 150 150 150 151 151 151 152 153 153 153 154 154 155 155 155 158 159 159 162
Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVDS Code Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Failure Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimizing NVDS Memory Usage for Execution Speed . . . . . . . . . . . . . . On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Unlock Sequence (8-Pin Devices Only) . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . .
163 163 163 164 165 165 165 167 167 167 168 168 169 170 170 171 171 172 172 172 177 177 178 180 180 180 180 182 183 185 185 185 185 187
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
191 191 192 192 194 199 212 212 213 217 219 224 226 227 228
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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List of Figures
Figure 1. Z8 Encore! XP(R) 4K Series Block Diagram . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Z8F04xA, Z8F02xA, and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Z8F04xA, Z8F02xA, and Z8F01xA in 20-Pin SOIC, SSOP or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Z8F04xA, Z8F02xA, and Z8F01xA in 28-Pin SOIC, SSOP or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 8. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 9. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 10. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 11. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . 91 Figure 12. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . 91 Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . 95 Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 97 Figure 15. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . 99 Figure 16. Infrared Data Communication System Block Diagram . . . . . . . . . 109 Figure 17. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 18. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 19. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . 114 Figure 20. Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 21. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 22. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . 139 Figure 23. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 24. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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Figure 25. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 26. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 27. Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . 186 Figure 28. Connecting the On-Chip Oscillator to an External RC Network . . . 188 Figure 29. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45KOhm Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 30. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 31. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 32. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 33. Typical Active Mode IDD Versus System Clock Frequency . . . . . . 216 Figure 34. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 35. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 36. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 37. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Figure 38. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Figure 39. 8-Pin Plastic Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . 230 Figure 40. 8-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . 231 Figure 41. 8-Pin Quad Flat No-Lead Package (QFN)/ MLF-S . . . . . . . . . . . . 232 Figure 42. 20-Pin Plastic Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . 233 Figure 43. 20-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . 234 Figure 44. 20-Pin Small Shrink Outline Package (SSOP) . . . . . . . . . . . . . . . . 235 Figure 45. 28-Pin Plastic Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . 236 Figure 46. 28-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . 237 Figure 47. 28-Pin Small Shrink Outline Package (SSOP) . . . . . . . . . . . . . . . . 238
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List of Tables
Table 1. Z8 Encore! XP(R) 4K Series Family Part Selection Guide . . . . . . . . . . . . 2 Table 2. Z8 Encore! XP(R) 4K Series Package Options. . . . . . . . . . . . . . . . . . . . . 7 Table 3. Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Pin Characteristics (20- and 28-pin Devices) . . . . . . . . . . . . . . . . . . . . 11 Table 5. Pin Characteristics (8-Pin Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Z8 Encore! XP(R)4K Series Series Program Memory Maps . . . . . . . . . 14 Table 7. Z8 Encore! XP(R)4K Series Flash Memory Information Area Map . . . . 15 Table 8. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Reset and STOP Mode Recovery Characteristics and Latency. . . . . . 21 Table 10. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . 22 Table 11. STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . 26 Table 12. Reset Status Register (RSTSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. Power Control Register 0 (PWRCTL0). . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . 32 Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) . . . . . . . . . . . . . . 36 Table 16. Port Alternate Function Mapping (8-Pin Parts). . . . . . . . . . . . . . . . . . 39 Table 17. GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . 40 Table 18. Port A-D GPIO Address Registers (PxADDR). . . . . . . . . . . . . . . . . . 41 Table 19. Port A-D Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20. Port A-D Data Direction Sub-Registers (PxDD) . . . . . . . . . . . . . . . . 42 Table 21. Port A-D Alternate Function Sub-Registers (PxAF). . . . . . . . . . . . . . 43 Table 22. Port A-D Output Control Sub-Registers (PxOC) . . . . . . . . . . . . . . . . 43 Table 23. Port A-D High Drive Enable Sub-Registers (PxHDE) . . . . . . . . . . . . 44 Table 24. Port A-D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 25. Port A-D Pull-Up Enable Sub-Registers (PxPUE) . . . . . . . . . . . . . . . 45 Table 26. Port A-D Alternate Function Set 1 Sub-Registers (PxAFS1). . . . . . . 45 Table 27. Port A-D Alternate Function Set 2 Sub-Registers (PxAFS2). . . . . . . 46
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Table 28. Port A-C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 29. Port A-D Output Data Register (PxOUT). . . . . . . . . . . . . . . . . . . . . . 47 Table 30. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 31. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . 48 Table 32. LED Drive Level Low Register (LEDLVLL). . . . . . . . . . . . . . . . . . . . . 48 Table 33. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . 51 Table 34. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 35. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 36. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 37. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 38. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . 57 Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL). . . . . . . . . . . . . . . . . . . . . 57 Table 40. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 41. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . 58 Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL). . . . . . . . . . . . . . . . . . . . . 59 Table 43. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 44. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . 59 Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL). . . . . . . . . . . . . . . . . . . . . 60 Table 46. Interrupt Edge Select Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . 60 Table 47. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . 61 Table 48. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 49. Timer 0-1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 50. Timer 0-1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 51. Timer 0-1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . 77 Table 52. Timer 0-1 Reload Low Byte Register (TxRL). . . . . . . . . . . . . . . . . . . 77 Table 53. Timer 0-1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . 77 Table 54. Timer 0-1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . 78 Table 55. Timer 0-1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . 78 Table 56. Timer 0-1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . 79 Table 57. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . 84
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Table 58. Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . 86 Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . 87 Table 60. Watch-Dog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . 87 Table 61. Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . 88 Table 62. UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . 100 Table 63. UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . 101 Table 64. UART Status 0 Register (U0STAT0) . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 65. UART Status 1 Register (U0STAT1) . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 66. UART Control 0 Register (U0CTL0). . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 67. UART Control 1 Register (U0CTL1). . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 68. UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . 106 Table 69. UART Baud Rate High Byte Register (U0BRH) . . . . . . . . . . . . . . . . 106 Table 70. UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . 106 Table 71. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 72. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 73. ADC Control/Status Register 1 (ADCCTL1). . . . . . . . . . . . . . . . . . . 126 Table 74. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . 127 Table 75. ADC Data Low Bits Register (ADCD_L). . . . . . . . . . . . . . . . . . . . . . 127 Table 76. ADC High Threshold High Byte (ADCTHH) . . . . . . . . . . . . . . . . . . . 128 Table 77. ADC Low Threshold High Byte (ADCTLH). . . . . . . . . . . . . . . . . . . . 128 Table 78. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . 131 Table 79. Z8 Encore! XP" 4K Series Flash Memory Configurations . . . . . . . . 136 Table 80. Flash Code Protection Using the Flash Option Bits . . . . . . . . . . . . . 141 Table 81. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 82. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 83. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 84. Flash Sector Protect Register (FPROT). . . . . . . . . . . . . . . . . . . . . . 146 Table 85. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . 147 Table 86. Flash Frequency Low Byte Register (FFREQL). . . . . . . . . . . . . . . . 147 Table 87. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . 150
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Table 88. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 89. Flash Option Bits at Program Memory Address 0000H . . . . . . . . . . 151 Table 90. Flash Options Bits at Program Memory Address 0001H . . . . . . . . . 152 Table 91. Trim Options Bits at Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 92. Trim Option Bits at 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 93. Trim Option Bits at 0002H (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 94. Trim Option Bits at Address 0003H (TLVD) . . . . . . . . . . . . . . . . . . . 154 Table 95. Trim Option Bits at 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 96. ADC Calibration Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 97. ADC Calibration Data Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 98. Watchdog Calibration High Byte at 007EH (WDTCALH) . . . . . . . . . 158 Table 99. Watchdog Calibration Low Byte at 007FH (WDTCALL). . . . . . . . . . 158 Table 100. Serial Number at 001C - 001F (S_NUM) . . . . . . . . . . . . . . . . . . . . 159 Table 101. Serialization Data Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 102. Lot Identification Number (RAND_LOT). . . . . . . . . . . . . . . . . . . . . 159 Table 103. Randomized Lot ID Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 104. Temperature Sensor Calibration High Byte at 003A (TSCALH). . . 162 Table 105. Temperature Sensor Calibration Low Byte at 003B (TSCALL) . . . 162 Table 106. Write Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 107. NVDS Read Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 108. OCD Baud-Rate Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 109. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 110. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 111. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . 181 Table 112. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . 183 Table 113. Recommended Crystal Oscillator Specifications. . . . . . . . . . . . . . 186 Table 114. Transconductance Values for Low, Medium, and High Gain Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 115. Assembly Language Syntax Example 1. . . . . . . . . . . . . . . . . . . . . 192 Table 116. Assembly Language Syntax Example 2. . . . . . . . . . . . . . . . . . . . . 192 Table 117. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
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Table 118. Additional Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 119. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 120. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 121. Block Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 122. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 123. Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 124. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 125. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 126. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 127. eZ8 CPU Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 128. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 129. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 130. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 131. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 132. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 133. Internal Precision Oscillator Electrical Characteristics . . . . . . . . . . 218 Table 134. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 135. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . 220 Table 136. Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . 220 Table 137. Analog-to-Digital Converter Electrical Characteristics and Timing. 221 Table 138. Non Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 139. Low Power Operational Amplifer Electrical Characteristics . . . . . . 223 Table 140. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 223 Table 141. Temperature Sensor Electrical Characteristics . . . . . . . . . . . . . . . 224 Table 142. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 143. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 144. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 145. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 146. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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Z8 Encore! XP(R) 4K Series Product Specification
1
Overview
The Z8 Encore!(R) MCU family of products are the first in a line of ZiLOG(R) microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP(R) 4K Series products expand upon ZiLOG's extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8(R) instructions. The rich peripheral set of the Z8 Encore! XP(R) 4K Series makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.
Features * * * * * * * * * * * * * * * * * * *
PS022815-0206
20 MHz eZ8 CPU 1KB, 2KB or 4KB Flash memory with in-circuit programming capability 256B, 512B or 1KB register RAM 16B to 128B non-volatile data storage (NVDS) Up to 20 vectored interrupts 6 to 25 I/O pins depending upon package Internal precision oscillator External crystal oscillator Full-duplex UART The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer Infrared Data Association (IrDA)-compliant infrared encoder/decoders, integrated with UART Two enhanced 16-bit timers with capture, compare, and PWM capability Watch-Dog Timer (WDT) with dedicated internal RC oscillator On-chip debugger Optional 8-channel, 10-bit analog-to-digital converter (ADC) Optional On-chip temperature sensor On-chip analog comparator Optional on-chip low-power operational amplifier (LPO) Voltage brown-out protection (VBO)
Overview
Z8 Encore! XP(R) 4K Series Product Specification
2
* * * * * * *
Programmable low battery detection (LVD) (8-pin devices only) Bandgap generated precision voltage references available for the ADC, comparator, VBO, and LVD. Power-on reset (POR) 2.7 V to 3.6 V operating voltage Up to thirteen 5V-tolerant input pins 8-, 20- and 28-pin packages 0 to +70C and -40 to +105C for operating temperature ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the Z8 Encore! XP(R) 4K Series product line.
Table 1. Z8 Encore! XP(R) 4K Series Family Part Selection Guide Part Number Z8F042A Z8F041A Z8F022A Z8F021A Z8F012A Z8F011A Flash (KB) 4 4 2 2 1 1 RAM (B) 1024 1024 512 512 256 256 EEPROM (B) 128 128 64 64 16 16 I/O 6-23 6-25 6-23 6-25 6-23 6-25 Advanced Comparator Analog* Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No ADC Inputs 4-8 0 4-8 0 4-8 0 Packages 8-, 20- and 28-pins 8-, 20- and 28-pins 8-, 20- and 28-pins 8-, 20- and 28-pins 8-, 20- and 28-pins 8-, 20- and 28-pins
Note: * Advanced Analog includes ADC, temperature sensor, and low-power operational amplifer.
Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8 Encore! XP(R) 4K Series devices.
PS022815-0206
Overview
Z8 Encore! XP(R) 4K Series Product Specification
3
System Clock
Oscillator Control
XTAL/RC Oscillator Internal Precision Oscillator Low Power RC Oscillator
On-Chip Debugger eZ8 CPU POR/VBO & Reset Controller
Interrupt Controller
WDT
Memory Busses Register Bus
Timers
UART
Comparator
ADC and LPO
NVDS Controller
Flash Controller
RAM Controller
IrDA
Temperature Sensor
Flash Memory
RAM
GPIO
Figure 1. Z8 Encore! XP(R) 4K Series Block Diagram
PS022815-0206
Overview
Z8 Encore! XP(R) 4K Series Product Specification
4
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8 CPU, ZiLOG(R)'s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8(R) instruction set. The eZ8 CPU features include:
* * * * * * * * * * *
Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8(R) code Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher-level programming languages, including C Pipelined instruction fetch and execution New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL New instructions support 12-bit linear addressing of the Register File Up to 10 MIPS operation C-Compiler friendly 2 to 9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
General Purpose I/O
The Z8 Encore! XP(R) 4K Series features 6 to 25 port pins (Ports A-D) for general purpose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports several protection mechanisms against accidental program and erasure.
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Overview
Z8 Encore! XP(R) 4K Series Product Specification
5
Non-Volatile Data Storage
The non-volatile data storage (NVDS) uses a hybrid hardware/software scheme to implement a byte programmable data memory and is capable of over 100,000 write cycles.
Internal Precision Oscillator
The internal precision oscillator (IPO) is a trimmable clock source that requires no external components.
Crystal Oscillator
The crystal oscillator circuit provides highly accurate clock frequencies with the use of an external crystal, ceramic resonator or RC network.
10-Bit Analog-to-Digital Converter
The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from eight different analog input pins in both single-ended and differential modes. The ADC also features a unity gain buffer when high input impedance is required.
Low-Power Operational Amplifier
The optional low-power operational amplifier (LPO) is a general-purpose amplifier primarily targeted for current sense applications. The LPO output may be routed internally to the ADC or externally to a pin.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal programmable voltage reference or a second input pin. The comparator output can be used to drive either an output pin or to generate an interrupt.
Temperature Sensor
The optional Temperature Sensor produces an analog output proportional to the device temperature. This signal can be sent to either the ADC or the analog comparator.
PS022815-0206
Overview
Z8 Encore! XP(R) 4K Series Product Specification
6
Low Battery Detector
The low battery detector (LVD) is able to generate an interrupt when the supply voltage drops below a user-programmable level. The LVD is available on 8-pin devices only.
UART
The UART is full-duplex and capable of handling asynchronous data transfers. The UART supports 8- and 9-bit data modes and selectable parity. The UART also supports multidrop address processing in hardware. The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer.
Timers
Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Capture Restart, Compare, Capture and Compare, PWM Single Output and PWM Dual Output modes.
Interrupt Controller
The Z8 Encore! XP(R) 4K Series products support up to 20 interrupts. These interrupts consist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources. The interrupts have 3 levels of programmable interrupt priority.
Reset Controller
The Z8 Encore! XP(R) 4K Series products can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT) time-out, STOP mode exit, or voltage brown-out (VBO) warning signal. The RESET pin is bi-directional, meaning it functions as reset source as well as a reset indicator.
On-Chip Debugger
The Z8 Encore! XP(R) 4K Series products feature an integrated on-chip debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming Flash memory, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.
PS022815-0206
Overview
Z8 Encore! XP(R) 4K Series Product Specification
7
Pin Description
Overview
The Z8 Encore! XP(R) 4K Series products are available in a variety of packages styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information regarding the physical package specifications, refer to the chapter Packaging on page 230.
Available Packages
Table 2 identifies the package styles that are available for each device in the Z8 Encore! XP(R) 4K Series product line.
Table 2. Z8 Encore! XP(R) 4K Series Package Options Part Number Z8F042A Z8F041A Z8F022A Z8F021A Z8F012A Z8F011A ADC Yes No Yes No Yes No 8-pin PDIP X X X X X X 8-pin SOIC X X X X X X 20-pin PDIP X X X X X X 20-pin SOIC X X X X X X 20-pin SSOP X X X X X X 28-pin PDIP X X X X X X 28-pin SOIC X X X X X X 28-pin 8-pin QFN/ SSOP MLF-S X X X X X X X X X X X X
Pin Configurations
Figures 2 through Figures 4 illustrate the pin configurations for all of the packages available in the Z8 Encore! XP(R) 4K Series. Refer to Table 3 for a description of the signals. The analog input alternate functions (ANAx) are not available on the Z8F041A, Z8F021A, and Z8F011A devices. The analog supply pins (AVDD and AVSS) are also not available on these parts, and are replaced by PB6 and PB7. At reset, all Port A, B and C pins default to an input state. In addition, any alternate functionality is not enabled, so the pins function as general purpose input ports until programmed otherwise. At powerup, the Port D0 pin defaults to the RESET alternate function.
PS022815-0206
Pin Description
Z8 Encore! XP(R) 4K Series Product Specification
8
The pin configurations listed are preliminary and subject to change based on manufacturing limitations.
VDD PA0/T0IN/T0OUT/XIN//DBG PA1/T0OUT/XOUT/ANA3/VREF/CLKIN PA2/RESET/DE0/T1OUT 1 2 3 4 8 7 6 5 VSS PA5/TXD0/T1OUT/ANA0/CINP/AMPOUT PA4/RXD0/ANA1/CINN/AMPINN PA3/CTS0/ANA2/COUT/AMPINP/T1IN
Figure 2.Z8F04xA, Z8F02xA, and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP Package
PB1/ANA1/AMPINN PB2/ANA2/AMPINP PB3/CLKIN/ANA3 VDD PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT VSS PA2/DE0 PA3/CTS0 PA4/RXD0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PB0/ANA0/AMPOUT PC3/COUT/LED PC2/ANA6/LED PC1/ANA5/CINN/LED PC0/ANA4/CINP/LED DBG RESET/PD0 PA7/T1OUT PA6/T1IN/T1OUT PA5/TXD0
Figure 3.Z8F04xA, Z8F02xA, and Z8F01xA in 20-Pin SOIC, SSOP or PDIP Package
PB2/ANA2/AMPINP PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 (PB6) AVDD VDD PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT VSS (PB7) AVSS PA2/DE0 PA3/CTS0 PA4/RXD0 PA5/TXD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PB1/ANA1/AMPINN PB0/ANA0/AMPOUT PC3/COUT/LED PC2/ANA6/LED PC1/ANA5/CINN/LED PC0/ANA4/CINP/LED DBG RESET/PD0 PC7/LED PC6/LED PA7/T1OUT PC5/LED PC4/LED PA6/T1IN/T1OUT
Figure 4.Z8F04xA, Z8F02xA, and Z8F01xA in 28-Pin SOIC, SSOP or PDIP Package
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Signal Descriptions
Table 3 describes the Z8 Encore! XP(R) 4K Series signals. Refer to the section Pin Configurations on page 7 to determine the signals available for the specific package styles.
Table 3. Signal Descriptions Signal Mnemonic I/O Description
General-Purpose I/O Ports A-D PA[7:0] PB[7:0] PC[7:0] PD[0] I/O I/O I/O I/O Port A. These pins are used for general-purpose I/O. Port B. These pins are used for general-purpose I/O. PB6 and PB7 are available only in those devices without an ADC. Port C. These pins are used for general-purpose I/O. Port D. This pin is used for general-purpose output only.
Note: PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are replaced by AVDD and AVSS. UART Controllers TXD0 RXD0 O I I O Transmit Data. This signal is the transmit output from the UART and IrDA. Receive Data. This signal is the receive input for the UART and IrDA. Clear To Send. This signal is the flow control input for the UART. Driver Enable. This signal allows automatic control of external RS-485 drivers. This signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART Status 0 register. The DE signal may be used to ensure the external RS-485 driver is enabled when data is transmitted by the UART.
CTS0
DE
Timers T0OUT/T1OUT T0OUT/T1OUT T0IN/T1IN Comparator CINP/CINN COUT I O Comparator Inputs. These signals are the positive and negative inputs to the comparator. Comparator Output. O O I Timer Output 0-1. These signals are outputs from the timers. Timer Complement Output 0-1. These signals are output from the timers in PWM Dual Output mode. Timer Input 0-1. These signals are used as the capture, gating and counter inputs.
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Table 3. Signal Descriptions (Continued) Signal Mnemonic Analog ANA[7:0] VREF I I/O Analog Port. These signals are used as inputs to the analog-to-digital converter (ADC). Analog-to-digital converter reference voltage input, or buffered output for internal reference. I/O Description
Low-Power Operational Amplifier (LPO) AMPINP/AMPINN AMPOUT Oscillators XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock. External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. I O LPO inputs. If enabled, these pins drive the positive and negative amplifier inputs respectively. LPO output. If enabled, this pin is driven by the on-chip LPO.
XOUT Clock Input CLKIN LED Drivers LED
O
I
Clock Input Signal. This pin may be used to input a TTL-level signal to be used as the system clock.
O
Direct LED drive capability. All port C pins have the capability to drive an LED without any other external components. These pins have programmable drive strengths set by the GPIO block.
On-Chip Debugger DBG I/O Debug. This signal is the control and data input and output to and from the On-Chip Debugger. The DBG pin is open-drain and requires an external pull-up resistor to ensure proper operation.
Caution:
Reset
RESET
I/O
RESET. Generates a Reset when asserted (driven Low). Also serves as a reset indicator; the Z8 Encore! XP(R) forces this pin low when in reset. This pin is open-drain and features an enabled internal pull-up resistor.
Power Supply VDD I Digital Power Supply.
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Table 3. Signal Descriptions (Continued) Signal Mnemonic AVDD VSS AVSS I/O I I I Description Analog Power Supply. Digital Ground. Analog Ground.
Note: The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and PB7 on 28-pin packages without ADC.
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on the Z8 Encore! XP(R) 4K Series 20- and 28-pin devices. Data in Table 4 is sorted alphabetically by the pin symbol mnemonic. Table 5 provides detailed information about the characteristics for each pin available on the Z8 Encore! XP(R) 4K Series 8-pin devices, Note: All six I/O pins on the 8-pin packages are 5V-tolerant (unless the pull-up devices are enabled). The column in Table 4 below describes 5V-tolerance for the 20 and 28-pin packages only.
Table 4. Pin Characteristics (20- and 28-pin Devices) Internal Pull- Schmitt Active Low Trigger or Tristate up Symbol Reset Mnemonic Direction Direction Active High Output or Pull-down Input
AVDD AVSS DBG PA[7:0] N/A N/A I/O I/O N/A N/A I I N/A N/A N/A N/A N/A N/A Yes Yes N/A N/A Yes Programmable Pull-up N/A N/A Yes Yes
Open Drain Output
N/A N/A Yes Yes, Programmable
5V Tolerance
N/A NA No PA[7:2] unless pullups enabled PB[7:6] unless pullups enabled PC[7:3] unless pullups enabled
PB[7:0]
I/O
I
N/A
Yes
Programmable Pull-up
Yes
Yes, Programmable
PC[7:0]
I/O
I
N/A
Yes
Programmable Pull-up
Yes
Yes, Programmable
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Table 4. Pin Characteristics (20- and 28-pin Devices) Active Low Internal Pull- Schmitt Symbol Reset or Tristate up Trigger Mnemonic Direction Direction Active High Output or Pull-down Input
RESET/ PD0 I/O I/O Low (in Yes (PD0 programmable (defaults to Reset mode) only) for PD0; RESET) always on for RESET N/A N/A N/A N/A N/A N/A Yes
Open Drain Output
programmable for PD0; always on for RESET N/A N/A
5V Tolerance
Yes, unless pullups enabled N/A N/A
VDD VSS
N/A N/A
Note:
)
PB6 and PB7 are available only in those devices without ADC.
Table 5. Pin Characteristics (8-Pin Devices)
Active Low Symbol Reset or Tristate Mnemonic Direction Direction Active High Output PA0/DBG I/O I (but can change during reset if key sequence detected) I N/A Yes
Internal Pull- Schmitt up Trigger or Pull-down Input Programmable Pull-up Yes
Open Drain Output Yes, Programmable
5V Tolerance Yes, unless pull-ups enabled
PA1
I/O
N/A
Yes
Programmable Pull-up
Yes
Yes, Programmable
Yes, unless pull-ups enabled Yes, unless pull-ups enabled Yes, unless pull-ups enabled N/A N/A
RESET/ PA2
I/O
I/O (defaults to RESET) I
Low (in Reset mode) N/A
Yes
Programmable for PA2; always on for RESET Programmable Pull-up
Yes
programmable for PA2; always on for RESET Yes, Programmable
PA[5:3]
I/O
Yes
Yes
VDD VSS
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
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Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
* * *
The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers. The Program Memory contains addresses for all memory locations having executable code and/or data. The Data Memory contains addresses for all memory locations that contain data only.
These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore!(R) MCU is 4KB (4096 bytes). The Register File is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as sources are read, and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256B control register section are reserved (unavailable). Reading from a reserved Register File address returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The Z8 Encore! XP(R) 4K Series devices contain 256B to 1KB of on-chip RAM. Reading from Register File addresses outside the available RAM addresses (and not within the control register address space) returns an undefined value. Writing to these Register File addresses produces no effect.
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Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8 Encore! XP(R) 4K Series devices contain 1KB to 4KB of on-chip Flash memory in the Program Memory address space, depending on the device. Reading from Program Memory addresses outside the available Flash memory addresses returns FFH. Writing to these unimplemented Program Memory addresses produces no effect. Table 6 describes the Program Memory Maps for the Z8 Encore! XP(R) 4K Series products.
Table 6. Z8 Encore! XP(R)4K Series Series Program Memory Maps Program Memory Address (Hex) Z8F042A and Z8F041A Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-0039 003A-003D 003E-0FFF Z8F022A and Z8F021A Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-0039 003A-003D 003E-07FF Z8F012A and Z8F011A Products 0000-0001 0002-0003 0004-0005 Flash Option Bits Reset Vector WDT Interrupt Vector Flash Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Reserved Oscillator Fail Trap Vectors Program Memory Flash Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Reserved Oscillator Fail Trap Vectors Program Memory Function
* See Table 33 on page 51 for a list of the interrupt vectors.
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Table 6. Z8 Encore! XP(R)4K Series Series Program Memory Maps (Continued) Program Memory Address (Hex) 0006-0007 0008-0037 0038-0039 003A-003D 003E-03FF Function Illegal Instruction Trap Interrupt Vectors* Reserved Oscillator Fail Trap Vectors Program Memory
* See Table 33 on page 51 for a list of the interrupt vectors.
Data Memory
The Z8 Encore! XP(R) 4K Series does not use the eZ8 CPU's 64KB Data Memory address space.
Flash Information Area
Table 7 describes the Z8 Encore! XP(R) 4K Series Flash Information Area. This 128B Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled, the Flash Information Area is mapped into the Program Memory and overlays the 128 bytes at addresses FE00H to FF7FH. When the Information Area access is enabled, all reads from these Program Memory addresses return the Information Area data rather than the Program Memory data. Access to the Flash Information Area is read-only.
Table 7. Z8 Encore! XP(R)4K Series Flash Memory Information Area Map Program Memory Address (Hex) FE00-FE3F FE40-FE53 Function ZiLOG Option Bits/Calibration Data Part Number 20-character ASCII alphanumeric code Left justified and filled with FFH Reserved ZiLOG Calibration Data Reserved
FE54-FE5F FE60-FE7F FE80-FFFF
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Register Map
Table 8 provides the address map for the Register File of the Z8 Encore! XP(R) 4K Series devices. Not all devices and package styles in the Z8 Encore! XP(R) 4K Series support the ADC, or all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved.
Table 8. Register File Address Map Address (Hex) Register Description Mnemonic Reset (Hex) Page #
General Purpose RAM Z8F042A/Z8F041A Devices 000-3FF 400-EFF 000-1FF 200-EFF 000-0FF 100-EFF Timer 0 F00 F01 F02 F03 F04 F05 F06 F07 Timer 1 F08 F09 F0A F0B F0C F0D XX=Undefined Timer 1 High Byte Timer 1 Low Byte Timer 1 Reload High Byte Timer 1 Reload Low Byte Timer 1 PWM High Byte Timer 1 PWM Low Byte T1H T1L T1RH T1RL T1PWMH T1PWML 00 01 FF FF 00 00 Timer 0 High Byte Timer 0 Low Byte Timer 0 Reload High Byte Timer 0 Reload Low Byte Timer 0 PWM High Byte Timer 0 PWM Low Byte Timer 0 Control 0 Timer 0 Control 1 T0H T0L T0RH T0RL T0PWMH T0PWML T0CTL0 T0CTL1 00 01 FF FF 00 00 00 00 General-Purpose Register File RAM Reserved General-Purpose Register File RAM Reserved General-Purpose Register File RAM Reserved -- -- -- -- -- -- XX XX XX XX XX XX
Z8F012A/Z8F021A Devices
Z8F022A/Z8F011A Devices
76 76 77 77 77 78 78 79 76 76 77 77 77 78
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Table 8. Register File Address Map (Continued) Address (Hex) F0E F0F F10-F6F UART F40 F41 F42 F43 F44 F45 F46 F47 F70 F71 F72 F73 F74 F75 F76 F77-F7F F80 F81 LED Controller F82 F83 F84 F85 F86 F87-F8F Comparator 0 F90 XX=Undefined Comparator 0 Control CMP0 14 LED Drive Enable LED Drive Level High Byte LED Drive Level Low Byte Reserved Oscillator Control Reserved LEDEN LEDLVLH LEDLVLL -- OSCCTL -- 00 00 00 XX A0 XX UART Transmit/Receive Data Registers UART Status 0 Register UART Control 0 Register UART Control 1 Register UART Status 1 Register UART Address Compare Register UART Baud Rate High Byte Register UART Baud Rate Low Byte Register ADC Control 0 ADC Control 1 ADC Data High Byte ADC Data Low Bits ADC High Threshold High Byte Reserved ADC Low Threshold High Byte Reserved Power Control 0 Reserved TXD, RXD U0STAT0 U0CTL0 U0CTL1 U0STAT1 U0ADDR U0BRH U0BRL ADCCTL0 ADCCTL1 ADCD_H ADCD_L ADCTHH -- ADCTLH -- PWRCTL0 -- XX 00 00 00 00 00 FF FF 00 80 XX XX FF XX 00 XX 80 XX Register Description Timer 1 Control 0 Timer 1 Control 1 Reserved Mnemonic T1CTL0 T1CTL1 -- Reset (Hex) 00 00 XX Page #
78 76
100 101 103 103 103 106 106 106 124 124 127 127 128 128
Analog-to-Digital Converter (ADC)
Low Power Control
31
47 48 48
Oscillator Control
183
131
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Table 8. Register File Address Map (Continued) Address (Hex) F91-FBF FC0 FC1 FC2 FC3 FC4 FC5 FC6 FC7 FC8 FC9-FCC FCD FCE FCF GPIO Port A FD0 FD1 FD2 FD3 GPIO Port B FD4 FD5 FD6 FD7 GPIO Port C FD8 FD9 FDA FDB GPIO Port D FDC FDD FDE XX=Undefined Port D Address Port D Control Reserved PDADDR PDCTL -- 00 00 XX Port C Address Port C Control Port C Input Data Port C Output Data PCADDR PCCTL PCIN PCOUT 00 00 XX 00 Port B Address Port B Control Port B Input Data Port B Output Data PBADDR PBCTL PBIN PBOUT 00 00 XX 00 Port A Address Port A Control Port A Input Data Port A Output Data PAADDR PACTL PAIN PAOUT 00 00 XX 00 Register Description Reserved Interrupt Request 0 IRQ0 Enable High Bit IRQ0 Enable Low Bit Interrupt Request 1 IRQ1 Enable High Bit IRQ1 Enable Low Bit Interrupt Request 2 IRQ2 Enable High Bit IRQ2 Enable Low Bit Reserved Interrupt Edge Select Shared Interrupt Select Interrupt Control Mnemonic -- IRQ0 IRQ0ENH IRQ0ENL IRQ1 IRQ1ENH IRQ1ENL IRQ2 IRQ2ENH IRQ2ENL -- IRQES IRQSS IRQCTL Reset (Hex) XX 00 00 00 00 00 00 00 00 00 XX 00 00 00 Page #
Interrupt Controller
55 57 57 56 58 59 56 59 60 61 61 61 40 42 42 42 40 42 42 42 40 42 42 42 40 42
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Table 8. Register File Address Map (Continued) Address (Hex) FDF FE0-FEF FF0 FF1 FF2 FF3 FF4-FF5 Trim Bit Control FF6 FF7 FF8 FF8 FF9 FFA FFB eZ8 CPU FFC FFD FFE FFF XX=Undefined Flags Register Pointer Stack Pointer High Byte Stack Pointer Low Byte -- RP SPH SPL XX XX XX XX Refer to the eZ8 CPU User Manual Trim Bit Address Trim Bit Data Flash Control Flash Status Flash Page Select Flash Sector Protect TRMADR TRMDR FCTL FSTAT FPS FPROT 00 00 00 00 00 00 00 00 Register Description Port D Output Data Reserved Reset Status (Read-only) Watch-Dog Timer Control (Write-only) Watch-Dog Timer Reload Upper Byte Watch-Dog Timer Reload High Byte Watch-Dog Timer Reload Low Byte Reserved Mnemonic PDOUT -- RSTSTAT WDTCTL WDTU WDTH WDTL -- Reset (Hex) 00 XX X0 N/A 00 04 00 XX Page #
42
Watch-Dog Timer (WDT)
27 86 87 87 88
150 151 144 145 146 146 147 147
Flash Memory Controller
Flash Programming Frequency High Byte FFREQH Flash Programming Frequency Low Byte FFREQL
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Z8 Encore! XP(R) 4K Series Product Specification
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Reset, STOP Mode Recovery and Low Voltage Detection
Overview
The Reset Controller within the Z8 Encore! XP(R) 4K Series controls Reset and STOP Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset:
* * * * * * * * * Reset Types
Power-on reset (POR) Voltage brown-out (VBO) Watch-Dog Timer time-out (when configured by the WDT_RES Flash Option Bit to initiate a reset) External RESET pin assertion (when the alternate RESET function is enabled by the GPIO register) On-chip debugger initiated Reset (OCDCTL[0] set to 1)
When the device is in STOP mode, a STOP Mode Recovery is initiated by either of the following: Watch-Dog Timer time-out GPIO Port input pin transition on an enabled STOP Mode Recovery source
The low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the following functions: Generates the VBO reset when the supply voltage drops below a minimum safe level Generates an interrupt when the supply voltage drops below a user-defined level (8-pin device only)
The Z8 Encore! XP(R) 4K Series provides several different types of Reset operation. STOP Mode Recovery is considered a form of Reset. Table 9 lists the types of Reset and their operating characteristics. The System Reset is longer if the external crystal oscillator is enabled by the Flash option bits, allowing additional time for oscillator start-up.
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Table 9. Reset and STOP Mode Recovery Characteristics and Latency Reset Characteristics and Latency Reset Type System Reset Control Registers Reset (as applicable) eZ8 CPU Reset Latency (Delay)
Reset 66 Internal Precision Oscillator Cycles Reset 5000 Internal Precision Oscillator Cycles Reset 66 Internal Precision Oscillator Cycles + IPO startup time Reset 5000 Internal Precision Oscillator Cycles
System Reset with Crystal Reset (as applicable) Oscillator Enabled STOP Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers
STOP Mode Recovery with Unaffected, except Crystal Oscillator Enabled WDT_CTL and OSC_CTL registers
During a System Reset or STOP Mode Recovery, the Internal Precision Oscillator requires 4 s to start up. Then the Z8 Encore! XP(R) 4K Series device is held in Reset for 66 cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because of a low voltage condition or power on reset, this delay is measured from the time that the supply voltage first exceeds the POR level (discussed later in this chapter). If the external pin reset remains asserted at the end of the reset period, the device remains in reset until the pin is deasserted. At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor disabled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset, the Port D0 pin is configured as a bidirectional open-drain reset. The pin is internally driven low during port reset, after which the user code may reconfigure this pin as a general purpose output. During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal oscillator and Watch-Dog Timer oscillator continue to run. Upon Reset, control registers within the Register File that have a defined Reset value are loaded with their reset values. Other control registers (including the Stack Pointer, Register Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address. Because the control registers are re-initialized by a system reset, the system clock after reset is always the IPO. User software must reconfigure the oscillator control block, such that the correct system clock source is enabled and selected.
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Reset Sources
Table 10 lists the possible sources of a system reset.
Table 10. Reset Sources and Resulting Reset Type Operating Mode NORMAL or HALT modes Reset Source Special Conditions
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage Out exceeds POR level Watch-Dog Timer time-out when configured for Reset RESET pin assertion None All reset pulses less than three system clocks in width are ignored.
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger (OCDCTL[0] set to 1) is unaffected by the reset STOP mode Power-On Reset / Voltage Brown- Reset delay begins after supply voltage Out exceeds POR level RESET pin assertion DBG pin driven Low All reset pulses less than the specified analog delay are ignored. See Table 134 on page 219 None
Power-On Reset
Z8 Encore! XP(R) 4K Series devices contain an internal power-on reset (POR) circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has timed out. If the crystal oscillator is enabled by the option bits, this timeout is longer. After the Z8 Encore! XP(R) 4K Series device exits the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1. Figure 5 illustrates Power-On Reset operation. Refer to the Electrical Characteristics on page 212 for the POR threshold voltage (VPOR).
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VCC = 3.3V VPOR VVBO
VCC = 0.0V
Program Execution
Internal Precision Oscillator
Crystal Oscillator Oscillator Start-up Internal RESET signal POR counter delay
Note: Not to Scale
optional XTAL counter delay
Figure 5.Power-On Reset Operation
Voltage Brown-Out Reset
The devices in the Z8 Encore! XP(R) 4K Series provide low voltage brown-out (VBO) protection. The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in the Reset. After the supply voltage again exceeds the Power-On Reset voltage threshold, the device progresses through a full System Reset sequence, as described in the Power-On Reset section. Following Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) register is set to 1. Figure 6 illustrates Voltage Brown-Out operation. Refer to the chapter Electrical Characteristics on page 212 for the VBO and POR threshold voltages (VVBO and VPOR). The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is set by the VBO_AO Flash Option Bit. Refer to the Flash Option Bits chapter for information about configuring VBO_AO.
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VCC = 3.3V VPOR VVBO Program Execution Voltage Brownout Program Execution
VCC = 3.3V
System Clock
Internal RESET signal
Note: Not to Scale
POR counter delay
Figure 6.Voltage Brown-Out Reset Operation
The POR level is greater than the VBO level by the specified hysteresis value. This ensures that the device undergoes a Power-On Reset after recovering from a VBO condition.
Watch-Dog Timer Reset
If the device is in NORMAL or STOP mode, the Watch-Dog Timer can initiate a System Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it configures the Watch-Dog Timer to cause an interrupt, not a System Reset, at time-out. The WDT bit in the Reset Status (RSTSTAT) register is set to signify that the reset was initiated by the Watch-Dog Timer.
External Reset Input
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. Once the RESET pin is asserted for a minimum of four system clock cycles, the device progresses through the System Reset sequence. Because of the possible asynchronicity of the system clock and reset signals, the required reset duration may be as short as three clock periods
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and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP(R) 4K Series devices remain in the Reset state. If the RESET pin is held Low beyond the System Reset timeout, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT status bit in the Reset Status (RSTSTAT) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see See Port A-D Control Registers on page 42.), the RESET pin functions as an open-drain (active low) reset mode indicator in addition to the input functionality. This reset output feature allows an Z8 Encore! XP(R) 4K Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO or WDT events. After an internal reset event occurs, the internal circuitry begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 9 has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset the POR bit in the WDT Control register is set.
STOP Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the chapter Low-Power Modes on page 29 for detailed STOP mode information. During STOP Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. The SMR delay (see Table 134 on page 219) TSMR, also includes the time required to start up the IPO. STOP Mode Recovery does not affect onchip registers other than the Watchdog Timer Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any STOP Mode Recovery, the IPO is enabled and selected as the system clock. If another system clock source is required, the STOP Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address. Following STOP Mode Recovery, the STOP bit in the Reset Status
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(RSTSTAT) Register is set to 1. Table 11 lists the STOP Mode Recovery sources and resulting actions. The text following provides more detailed information about each of the STOP Mode Recovery sources.
Table 11. STOP Mode Recovery Sources and Resulting Action Operating Mode STOP mode STOP Mode Recovery Source Watch-Dog Timer time-out when configured for Reset Watch-Dog Timer time-out when configured for interrupt Data transition on any GPIO Port pin enabled as a STOP Mode Recovery source Assertion of external RESET Pin Debug Pin driven Low Action STOP Mode Recovery STOP Mode Recovery followed by interrupt (if interrupts are enabled) STOP Mode Recovery
System Reset System Reset
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP Mode Recovery sequence. In the Reset Status (RSTSTAT) register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon timeout and the Z8 Encore! XP(R) 4K Series device is configured to respond to interrupts, the eZ8 CPU services the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates STOP Mode Recovery. Note that SMR pulses shorter than specified will not trigger a recovery. (See Table 134 on page 219). When this happens, the STOP bit in the Reset Status (RSTSTAT) register is set to 1. Caution: In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay. As a result, short pulses on the Port pin can initiate STOP Mode Recovery without being written to the Port Input Data register or without initiating an interrupt (if enabled for that pin).
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STOP Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP(R) 4K Series device is in STOP Mode and the external RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See Electrical Characteristics on page 212 for details.
Low Voltage Detection
In addition to the Voltage Brown-out Reset (VBO) described above, it is also possible to generate an interrupt when the supply voltage drops below a user-selected value. See Trim Bit Address 0003H on page 154. for details about the Low Voltage Detection (LVD) threshold levels available. The LVD function is available on the 8-pin product versions only. When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status (RSTSTAT) register is set to one. This bit remains one until the low-voltage condition goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate an interrupt when so enabled. (See Interrupt Vectors and Priority on page 53.) The LVD bit is NOT latched, so enabling the interrupt is the only way to guarantee detection of a transient low voltage event. The LVD functionality depends on circuitry shared with the VBO block; therefore disabling the VBO also disables the LVD.
Reset Register Definitions
Reset Status Register
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0. This register shares its address with the Watch-Dog Timer control register, which is writeonly (Table 12).
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Table 12. Reset Status Register (RSTSTAT) BITS FIELD RESET R/W ADDR Reset or STOP Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watch-Dog Timer time-out Reset using the On-Chip Debugger (OCTCTL[1] set to 1) Reset from STOP Mode using DBG Pin driven Low STOP Mode Recovery using GPIO pin transition STOP Mode Recovery using Watch-Dog Timer time-out 7 POR R 6 STOP R 5 WDT R 4 EXT 0 R FF0H POR 1 0 0 1 1 0 0 STOP 0 0 0 0 0 1 1 WDT 0 0 1 0 0 0 1 EXT 0 1 0 0 0 0 0 0 R 3 2 Reserved 0 R 0 R 1 0 LVD 0 R
See descriptions below
POR--Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT timeout or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP--STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred because of a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT--Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. This read must occur before clearing the WDT interrupt. EXT--External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. Reserved--Must be 0. LVD--Low Voltage Detection Indicator If this bit is set to 1 the current state of the supply voltage is below the low voltage detection threshold. This value is not latched but is a real-time indicator of the supply voltage level.
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Low-Power Modes
Overview
The Z8 Encore! XP(R) 4K Series products contain power-saving features. The highest level of power reduction is provided by the STOP mode. The next lower level of power reduction is provided by the HALT mode. Further power savings can be implemented by disabling individual peripheral blocks while in Active mode (defined as being in neither STOP nor HALT mode).
STOP Mode
Executing the eZ8 CPU's STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are:
* * * * * * * * *
Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the GPIO registers. System clock is stopped. eZ8 CPU is stopped. Program counter (PC) stops incrementing. Watch-Dog Timer's internal RC oscillator continues to operate if enabled by the Oscillator Control Register. If enabled, the Watch-Dog Timer logic continues to operate. If enabled for operation in STOP mode by the associated Flash Option Bit, the VoltageBrown Out protection circuit continues to operate. Low-power operational amplifier continues to operate if enabled by the Power Control Register to do so. All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs configured as outputs should also be driven to one of the supply rails. The device can be brought out of STOP mode using STOP Mode Recovery. For more information about STOP Mode Recovery refer to Reset, STOP Mode Recovery and Low Voltage Detection on page 20.
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HALT Mode
Executing the eZ8 CPU's HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are:
* * * * * * * * * * * *
Primary oscillator is enabled and continues to operate. System clock is enabled and continues to operate. eZ8 CPU is stopped. Program counter (PC) stops incrementing. Watch-Dog Timer's internal RC oscillator continues to operate. If enabled, the Watch-Dog Timer continues to operate. All other on-chip peripherals continue to operate, if enabled. Interrupt Watch-Dog Timer time-out (interrupt or reset) Power-On reset Voltage-Brown out reset External RESET pin assertion
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the STOP and Halt modes, it is possible to disable each peripheral on each of the Z8 Encore! XP(R) 4K Series devices. Disabling a given peripheral minimizes its power consumption.
Power Control Register Definitions
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. The default state of the low-power operational amplifier (LPO) is OFF. To use the LPO, clear the LPO bit, turning it ON. Clearing this bit might interfere with normal ADC mea-
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surements on ANA0 (the LPO output). This bit enables the amplifier even in STOP mode. If the amplifier is not required in STOP mode, disable it. Failure to perform this results in STOP mode currents greater than specified. Note: This register is only reset during a power-on reset sequence. Other system reset events do not affect it.
Table 13. Power Control Register 0 (PWRCTL0) BITS FIELD RESET R/W ADDR 7 LPO 1 R/W 6 Reserved 0 R/W 0 R/W 5 4 VBO 0 R/W F80H 3 TEMP 0 R/W 2 ADC 0 R/W 1 COMP 0 R/W 0 Reserved 0 R/W
LPO -- Low-Power Operational Amplifier Disable 0 = LPO is enabled (this applies even in STOP mode). 1 = LPO is disabled. Reserved--Must be 0. VBO--Voltage Brown-Out Detector Disable This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active. 0 = VBO Enabled 1 = VBO Disabled TEMP--Temperature Sensor Disable 0 = Temperature Sensor Enabled 1 = Temperature Sensor Disabled ADC--Analog-to-Digital Converter Disable 0 = Analog-to-Digital Converter Enabled 1 = Analog-to-Digital Converter Disabled COMP--Comparator Disable 0 = Comparator is Enabled 1 = Comparator is Disabled Reserved--Must be 0. Note: Asserting any power control bit will disable the targeted block, regardless of any enable bits contained in the target block's control registers.
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General-Purpose I/O
Overview
The Z8 Encore! XP(R) 4K Series products support a maximum of 25 port pins (Ports A-D) for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, STOP Mode Recovery functionality, and alternate pin functions. Each port pin is individually programmable. In addition, the Port C pins are capable of direct LED drive at programmable drive strengths.
GPIO Port Availability By Device
Table 14 lists the port pins available with each device and package type.
Table 14. Port Availability by Device and Package Type Devices Z8F042ASB, Z8F042APB, Z8F042AQB Z8F022ASB, Z8F022APB, Z8F022AQB Z8F012ASB, Z8F012APB, Z8F012AQB Z8F041ASB, Z8F041APB, Z8F041AQB Z8F021ASB, Z8F021APB, Z8F021AQB Z8F011ASB, Z8F011APB, Z8F011AQB Z8F042APH, Z8F042AHH, Z8F042ASH Z8F022APH, Z8F022AHH, Z8F022ASH Z8F012APH, Z8F012AHH, Z8F012ASH Z8F041APH, Z8F041AHH, Z8F041ASH Z8F021APH, Z8F021AHH, Z8F021ASH Z8F011APH, Z8F011AHH, Z8F011ASH Z8F042APJ, Z8F042ASJ, Z8F042AHJ Z8F022APJ, Z8F022ASJ, Z8F022AHJ Z8F012APJ, Z8F012ASJ, Z8F012AHJ Z8F041APJ, Z8F041ASJ, Z8F041AHJ Z8F021APJ, Z8F021ASJ, Z8F021AHJ Z8F011APJ, Z8F011ASJ, Z8F011AHJ Package 10-Bit ADC Port A Port B Port C Port D Total I/O 8-pin Yes [5:0] No No No 6
8-pin
No
[5:0]
No
No
No
6
20-pin
Yes
[7:0]
[3:0]
[3:0]
[0]
17
20-pin
No
[7:0]
[3:0]
[3:0]
[0]
17
28-pin
Yes
[7:0]
[5:0]
[7:0]
[0]
23
28-pin
No
[7:0]
[7:0]
[7:0]
[0]
25
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Architecture
Figure 7 illustrates a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not illustrated.
Port Input Data Register Q D Q D Schmitt Trigger
System Clock VDD Port Output Control Port Output Data Register DATA Bus System Clock D Q Port Pin
Port Data Direction
GND
Figure 7.GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip peripheral functions such as the timers and serial communication devices. The Port A-D Alternate Function sub-registers configure these pins for either General-Purpose I/O or alternate function operation. When a pin is configured for alternate function, control of the port pin direction (input/output) is passed from the Port A-D Data Direction registers to the alternate function assigned to this pin. Table 15 on page 36 lists the alternate functions possible with each port pin. For those pins with more one alternate function, the alternate function is defined through Alternate Function Sets sub-registers AFS1 and AFS2. The crystal oscillator functionality is not controlled by the GPIO block. When the crystal oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1 is overridden. In that case, those pins function as input and output for the crystal oscillator.
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PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. See Timers on page 62 for more details.
Direct LED Drive
The Port C pins provide a current sinked output capable of driving an LED without requiring an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA, 13 mA and 20 mA. This mode is enabled through the Alternate Function sub-register AFS1 and is programmable through the LED control registers. The LED Drive Enable (LEDEN) register turns on the drivers. The LED Drive Level (LEDLVLH and LEDLVLL) registers select the sink current. For correct function, the LED anode must be connected to VDD and the cathode to the GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in excessive total current. Refer to the Electrical Characteristics on page 212 for the maximum total current for the applicable package.
Shared Reset Pin
On the 20 and 28-pin devices, the Port D0 pin shares function with a bi-directional reset pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin acts as a bi-directional reset until user software re-configures it. The Port D0 pin is output-only when in GPIO mode. On the 8-pin product versions, the reset pin is shared with PortA2, but the pin is not limited to output-only when in GPIO mode. Caution: If PA2 on the 8-pin product is reconfigured as an input, take care that no external stimulus drives the pin low during any reset sequence. Since PA2 returns to its RESET alternate function during system resets, driving it low will hold the chip in a reset state until the pin is released. The same applies to the PDO pin on the 28-pin product.
Shared Debug Pin
On the 8-pin version of this device only, the Debug pin shares function with the PortA0 GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. If the unlock sequence is present, the debug function is unlocked and the pin no longer functions as a GPIO pin. If it is not present, the debug feature is disabled until/ unless another reset event occurs. For more details, see On-Chip Debugger on page 167
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Crystal Oscillator Override
For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When the crystal oscillator is enabled (see Oscillator Control Register Definitions on page 183), the GPIO settings are overridden and PA0 and PA1 are disabled.
5V Tolerance
All six I/O pins on the 8-pin devices are 5V-tolerant, unless the programmable pull-ups are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these parts, excessive current flows through those pull-up devices and can damage the chip. Note: In the 20- and 28-pin versions of this device, any pin which shares functionality with an ADC, crystal or comparator port is not 5V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5V-tolerant, and can safely handle inputs higher than VDD except when the programmable pull-ups are enabled.
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator Control (OSCCTL)Register (page 183) such that the external oscillator is selected as the system clock. For 8-pin devices use PA1 instead of PB3.
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Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) Alternate Function Set Register AFS1
Port Port A
Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
Mnemonic T0IN/T0OUT* Reserved T0OUT Reserved DE0 Reserved CTS0 Reserved RXD0/IRRX0 Reserved TXD0/IRTX0 Reserved T1IN/T1OUT* Reserved T1OUT Reserved
Alternate Function Description
Timer 0 Input/Timer 0 Output Complement N/A Timer 0 Output UART 0 Driver Enable UART 0 Clear to Send UART 0 / IrDA 0 Receive Data UART 0 / IrDA 0 Transmit Data Timer 1 Input/Timer 1 Output Complement Timer 1 Output
Note: Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not implemented for Port A. Enabling alternate function selections as described in Port A-D Alternate Function Sub-Registers on page 42 automatically enables the associated alternate function. * Whether PA0/PA6 take on the timer input or timer output complement function depends on the timer configuration as described in Timer Pin Signal Operation on page 75.
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Table 15. Port Alternate Function Mapping (Continued)(Non 8-Pin Parts) Alternate Function Set Register AFS1 AFS1[0]: 0 ADC Analog Input/LPO Output ADC Analog Input/LPO Input (N) ADC Analog Input/LPO Input (P) External Clock Input ADC Analog Input ADC Analog Input ADC Voltage Reference AFS1[0]: 1 AFS1[1]: 0 AFS1[1]: 1 AFS1[2]: 0 AFS1[2]: 1 AFS1[3]: 0 AFS1[3]: 1 AFS1[4]: 0 AFS1[4]: 1 AFS1[5]: 0 AFS1[5]: 1 AFS1[6]: 0 AFS1[6]: 1 AFS1[7]: 0 AFS1[7]: 1
Port Port B
Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Mnemonic Reserved ANA0/AMPOUT Reserved ANA1/AMPINN Reserved ANA2/AMPINP CLKIN ANA3 Reserved ANA7 Reserved VREF* Reserved Reserved Reserved Reserved
Alternate Function Description
Note: Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set register AFS2 is not used to select the function. Also, alternate function selection as described in Port A-D Alternate Function Sub-Registers on page 42 must also be enabled. * VREF is available on PB5 in 28-pin products only.
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Table 15. Port Alternate Function Mapping (Continued)(Non 8-Pin Parts) Alternate Function Set Register AFS1 AFS1[0]: 0 AFS1[0]: 1 AFS1[1]: 0 AFS1[1]: 1 AFS1[2]: 0 ADC Analog Input, LED Drive, or ADC Voltage Reference Comparator Output LED drive LED Drive LED Drive LED Drive AFS1[2]: 1 AFS1[3]: 0 AFS1[3]: 1 AFS1[4]: 0 AFS1[4]: 1 AFS1[5]: 0 AFS1[5]: 1 AFS1[6]: 0 AFS1[6]: 1 AFS1[7]: 0 LED Drive AFS1[7]: 1
Port Port C
Pin PC0
Mnemonic Reserved
Alternate Function Description
ANA4/CINP/LED ADC or Comparator Input, or LED drive Drive PC1 Reserved ANA5/CINN/ LED ADC or Comparator Input, or LED drive Drive PC2 Reserved ANA6/LED/ VREF* PC3 PC4 PC5 PC6 COUT LED Reserved LED Reserved LED Reserved LED PC7 Reserved LED
Note: Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set register AFS2 is not used to select the function. Also, alternate function selection as described in Port A-D Alternate Function Sub-Registers on page 42 must also be enabled. * VREF is available on PC2 in 20-pin products only.
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Table 16. Port Alternate Function Mapping (8-Pin Parts) Alternate Function Select Register AFS1 AFS1[0]: 0 AFS1[0]: 0 AFS1[0]: 1 Timer 0 Output Complement Timer 0 Output External Clock Input UART 0 Driver Enable External Reset Timer 1 Output UART 0 Clear to Send Comparator Output Timer 1 Input AFS1[0]: 1 AFS1[1]: 0 AFS1[1]: 0 AFS1[1]: 1 AFS1[1]: 1 AFS1[2]: 0 AFS1[2]: 0 AFS1[2]: 1 AFS1[2]: 1 AFS1[3]: 0 AFS1[3]: 0 AFS1[3]: 1 AFS1[3]: 1 AFS1[4]: 0 AFS1[4]: 0 AFS1[4]: 1 Alternate Function Select Register AFS2 AFS1[0]: 0 AFS2[0]: 1 AFS2[0]: 0 AFS2[0]: 1 AFS2[1]: 0 AFS2[1]: 1 AFS2[1]: 0 AFS2[1]: 1 AFS2[2]: 0 AFS2[2]: 1 AFS2[2]: 0 AFS2[2]: 1 AFS2[3]: 0 AFS2[3]: 1 AFS2[3]: 0 AFS2[3]: 1 AFS2[4]: 0 AFS2[4]: 1 AFS2[4]: 0 AFS2[4]: 1 AFS2[5]: 0 AFS2[5]: 1
Port Port A
Pin PA0
Mnemonic T0IN Reserved Reserved T0OUT
Alternate Function Description Timer 0 Input
PA1
T0OUT Reserved CLKIN
Analog Functions* ADC Analog Input/VREF PA2 DE0 RESET T1OUT Reserved PA3 CTS0 COUT T1IN
Analog Functions* ADC Analog Input/LPO Input (P) PA4 RXD0 Reserved Reserved UART 0 Receive Data
Analog Functions* ADC/Comparator Input (N)/LPO AFS1[4]: 1 Input (N) PA5 TXD0 T1OUT UART 0 Transmit Data Timer 1 Output Complement AFS1[5]: 0 AFS1[5]: 0
* Analog Functions include ADC inputs, ADC reference, comparator inputs and LPO ports.
Note: Also, alternate function selection as described in Port A-D Alternate Function Sub-Registers on page must be enabled.
42
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Table 16. Port Alternate Function Mapping (8-Pin Parts) (Continued) Alternate Function Select Register AFS1 AFS2[5]: 1 Alternate Function Select Register AFS2 AFS1[5]: 0 AFS1[5]: 1
Port Port A (Cont)
Pin
Mnemonic Reserved
Alternate Function Description
Analog Functions* ADC/Comparator Input (P) LPO AFS2[5]: 1 Output
Note: Also, alternate function selection as described in Port A-D Alternate Function Sub-Registers on page must be enabled.
* Analog Functions include ADC inputs, ADC reference, comparator inputs and LPO ports.
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GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins can be configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). Refer to the chapter Interrupt Controller on page 50 for more information about interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data. Table 17 lists these Port registers. Use the Port A-D Address and Control registers together to provide access to sub-registers for Port configuration and control.
Table 17. GPIO Port Registers and Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic PxDD PxAF Port Register Name Port A-D Address Register (Selects sub-registers) Port A-D Control Register (Provides access to sub-registers) Port A-D Input Data Register Port A-D Output Data Register Port Register Name Data Direction Alternate Function
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Table 17. GPIO Port Registers and Sub-Registers (Continued) Port Register Mnemonic PxOC PxHDE PxSMRE PxPUE PxAFS1 PxAFS2 Port Register Name Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable Pull-up Enable Alternate Function Set 1 Alternate Function Set 2
Port A-D Address Registers
The Port A-D Address registers select the GPIO Port functionality accessible through the Port A-D Control registers. The Port A-D Address and Control registers combine to provide access to all GPIO Port controls (Table 18).
Table 18. Port A-D GPIO Address Registers (PxADDR) BITS FIELD RESET R/W ADDR R/W R/W R/W R/W 7 6 5 4 00H R/W R/W R/W R/W FD0H, FD4H, FD8H, FDCH 3 2 1 0
PADDR[7:0]
PADDR[7:0]--Port Address The Port Address selects one of the sub-registers accessible through the Port Control register.
PADDR[7:0] 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H-FFH Port Control sub-register accessible using the Port A-D Control Registers No function. Provides some protection against accidental Port reconfiguration. Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable. Pull-up Enable Alternate Function Set 1 Alternate Function Set 2 No function
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Port A-D Control Registers
The Port A-D Control registers set the GPIO port operation. The value in the corresponding Port A-D Address register determines which sub-register is read from or written to by a Port A-D Control register transaction (Table 19).
Table 19. Port A-D Control Registers (PxCTL) BITS FIELD RESET R/W ADDR R/W R/W R/W R/W 7 6 5 4 PCTL 00H R/W R/W R/W R/W FD1H, FD5H, FD9H, FDDH 3 2 1 0
PCTL[7:0]--Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation.
Port A-D Data Direction Sub-Registers
The Port A-D Data Direction sub-register is accessed through the Port A-D Control register by writing 01H to the Port A-D Address register (Table 20).
Table 20. Port A-D Data Direction Sub-Registers (PxDD) BITS FIELD RESET R/W ADDR 7 DD7 1 R/W 6 DD6 1 R/W 5 DD5 1 R/W 4 DD4 1 R/W 3 DD3 1 R/W 2 DD2 1 R/W 1 DD1 1 R/W 0 DD0 1 R/W
If 01H in Port A-D Address Register, accessible through the Port A-D Control Register
DD[7:0]--Data Direction These bits control the direction of the associated port pin. Port Alternate Function operation overrides the Data Direction register setting. 0 = Output. Data in the Port A-D Output Data register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A-D Input Data Register. The output driver is tristated.
Port A-D Alternate Function Sub-Registers
The Port A-D Alternate Function sub-register (Table 21) is accessed through the Port A- D Control register by writing 02H to the Port A-D Address register. The Port A-D Alternate Function sub-registers enable the alternate function selection on pins. If disabled, pins
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functions as GPIO. If enabled, select one of four alternate functions using alternate function set subregisters 1 and 2 as described in the Port A-D Alternate Function Set 1 SubRegisters on page 45 and Port A-D Alternate Function Set 2 Sub-Registers on page 46. Refer to the GPIO Alternate Functions on page 33 to determine the alternate function associated with each port pin. Caution: Do not enable alternate functions for GPIO port pins for which there is no associated alternate function. Failure to follow this guideline can result in unpredictable operation.
Table 21. Port A-D Alternate Function Sub-Registers (PxAF) BITS FIELD RESET R/W ADDR 7 AF7 6 AF6 5 AF5 4 AF4 R/W If 02H in Port A-D Address Register, accessible through the Port A-D Control Register 3 AF3 2 AF2 1 AF1 0 AF0
00H (Ports A-C); 01H (Port D); 04H (Port A of 8-pin device)
AF[7:0]--Port Alternate Function enabled 0 = The port pin is in normal mode and the DDx bit in the Port A-D Data Direction subregister determines the direction of the pin. 1 = The alternate function selected through Alternate Function Set sub-registers is enabled. Port pin operation is controlled by the alternate function. Port A-D Output Control Sub-Registers The Port A-D Output Control sub-register (Table 22) is accessed through the Port A-D Control register by writing 03H to the Port A-D Address register. Setting the bits in the Port A-D Output Control sub-registers to 1 configures the specified port pins for opendrain operation. These sub-registers affect the pins directly and, as a result, alternate functions are also affected.
Table 22. Port A-D Output Control Sub-Registers (PxOC) BITS FIELD RESET R/W ADDR 7 POC7 0 R/W 6 POC6 0 R/W 5 POC5 0 R/W 4 POC4 0 R/W 3 POC3 0 R/W 2 POC2 0 R/W 1 POC1 0 R/W 0 POC0 0 R/W
If 03H in Port A-D Address Register, accessible through the Port A-D Control Register
POC[7:0]--Port Output Control These bits function independently of the alternate function bit and always disable the
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drains if set to 1. 0 = The source current is enabled for any output mode (unless overridden by the alternate function). (Push-pull output) 1 = The source current for the associated pin is disabled (open-drain mode). Port A-D High Drive Enable Sub-Registers The Port A-D High Drive Enable sub-register (Table 23) is accessed through the Port A-D Control register by writing 04H to the Port A-D Address register. Setting the bits in the Port A-D High Drive Enable sub-registers to 1 configures the specified port pins for high current output drive operation. The Port A-D High Drive Enable sub-register affects the pins directly and, as a result, alternate functions are also affected.
Table 23. Port A-D High Drive Enable Sub-Registers (PxHDE) BITS FIELD RESET R/W ADDR 7 PHDE7 0 R/W 6 PHDE6 0 R/W 5 PHDE5 0 R/W 4 PHDE4 0 R/W 3 PHDE3 0 R/W 2 PHDE2 0 R/W 1 PHDE1 0 R/W 0 PHDE0 0 R/W
If 04H in Port A-D Address Register, accessible through the Port A-D Control Register
PHDE[7:0]--Port High Drive Enabled 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. Port A-D STOP Mode Recovery Source Enable Sub-Registers The Port A-D STOP Mode Recovery Source Enable sub-register (Table 24) is accessed through the Port A-D Control register by writing 05H to the Port A-D Address register. Setting the bits in the Port A-D STOP Mode Recovery Source Enable sub-registers to 1 configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode, any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates STOP Mode Recovery.
Table 24. Port A-D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE) BITS FIELD RESET R/W ADDR 7 PSMRE7 0 R/W 6 PSMRE6 0 R/W 5 PSMRE5 0 R/W 4 PSMRE4 0 R/W 3 PSMRE3 0 R/W 2 PSMRE2 0 R/W 1 PSMRE1 0 R/W 0 PSMRE0 0 R/W
If 05H in Port A-D Address Register, accessible through the Port A-D Control Register
PSMRE[7:0]--Port STOP Mode Recovery Source Enabled 0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
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pin during STOP mode do not initiate STOP Mode Recovery. 1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on this pin during STOP mode initiates STOP Mode Recovery. Port A-D Pull-up Enable Sub-Registers The Port A-D Pull-up Enable sub-register (Table 25) is accessed through the Port A-D Control register by writing 06H to the Port A-D Address register. Setting the bits in the Port A-D Pull-up Enable sub-registers enables a weak internal resistive pull-up on the specified Port pins.
Table 25. Port A-D Pull-Up Enable Sub-Registers (PxPUE) BITS FIELD RESET R/W ADDR 7 PPUE7 0 R/W 6 PPUE6 0 R/W 5 PPUE5 0 R/W 4 PPUE4 0 R/W 3 PPUE3 0 R/W 2 PPUE2 0 R/W 1 PPUE1 0 R/W 0 PPUE0 0 R/W
If 06H in Port A-D Address Register, accessible through the Port A-D Control Register
PPUE[7:0]--Port Pull-up Enabled 0 = The weak pull-up on the Port pin is disabled. 1 = The weak pull-up on the Port pin is enabled. Port A-D Alternate Function Set 1 Sub-Registers The Port A-D Alternate Function Set1 sub-register (Table 26) is accessed through the Port A-D Control register by writing 07H to the Port A-D Address register. The Alternate Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate Functions selected by setting or clearing bits of this register are defined in GPIO Alternate Functions on page 33. Note: Alternate function selection on port pins must also be enabled as decribed in Port A-D Alternate Function Sub-Registers on page 42.
Table 26. Port A-D Alternate Function Set 1 Sub-Registers (PxAFS1) BITS FIELD RESET R/W ADDR R/W 7 PAFS17 6 PAFS16 R/W 5 PAFS15 R/W 4 PAFS14 R/W 3 PAFS13 R/W 2 PAFS12 R/W 1 PAFS11 R/W 0 PAFS10 R/W
00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device) If 07H in Port A-D Address Register, accessible through the Port A-D Control Register
PAFS1[7:0]--Port Alternate Function Set 1 0 = Port Alternate Function selected as defined in Tables 15 and 16 in the GPIO Alternate
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Functions section. 1 = Port Alternate Function selected as defined in Tables 15 and 16 in the GPIO Alternate Functions section. Port A-D Alternate Function Set 2 Sub-Registers The Port A-D Alternate Function Set 2 sub-register (Table 27) is accessed through the Port A-D Control register by writing 08H to the Port A-D Address register. The Alternate Function Set 2 sub-registers selects the alternate function available at a port pin. Alternate Functions selected by setting or clearing bits of this register is defined in Table 16 in the section GPIO Alternate Functions on page 33. Note: Alternate function selection on port pins must also be enabled as decribed in Port A-D Alternate Function Sub-Registers on page 42.
Table 27. Port A-D Alternate Function Set 2 Sub-Registers (PxAFS2) BITS FIELD RESET R/W ADDR R/W 7 PAFS27 6 PAFS26 R/W 5 PAFS25 R/W 4 PAFS24 R/W 3 PAFS23 R/W 2 PAFS22 R/W 1 PAFS21 R/W 0 PAFS20 R/W
00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device) If 08H in Port A-D Address Register, accessible through the Port A-D Control Register
PAFS2[7:0]--Port Alternate Function Set 2 0 = Port Alternate Function selected as defined in Table 16 GPIO Alternate Functions section. 1 = Port Alternate Function selected as defined in Table 16 GPIO Alternate Functions section.
Port A-C Input Data Registers
Reading from the Port A-C Input Data registers (Table 28) returns the sampled values from the corresponding port pins. The Port A-C Input Data registers are read-only. The value returned for any unused ports is 0. Unused ports include those missing on the 8- and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 28. Port A-C Input Data Registers (PxIN)
BITS FIELD RESET R/W ADDR 7 6 5 4 3 2 1 0
PIN7 X R
PIN6 X R
PIN5 X R
PIN4 X R
PIN3 X R
PIN2 X R
PIN1 X R
PIN0 X R
FD2H, FD6H, FDAH
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PIN[7:0]--Port Input Data Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High).
Port A-D Output Data Register
The Port A-D Output Data register (Table 29) controls the output data to the pins.
Table 29. Port A-D Output Data Register (PxOUT) BITS FIELD RESET R/W ADDR 7 POUT7 0 R/W 6 POUT6 0 R/W 5 POUT5 0 R/W 4 POUT4 0 R/W 3 POUT3 0 R/W 2 POUT2 0 R/W 1 POUT1 0 R/W 0 POUT0 0 R/W
FD3H, FD7H, FDBH, FDFH
POUT[7:0]--Port Output Data These bits contain the data to be driven to the port pins. The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = Drive a logical 0 (Low). 1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting the corresponding Port Output Control register bit to 1.
LED Drive Enable Register
The LED Drive Enable register (Table 30) activates the controlled current drive. The Port C pin must first be enabled by setting the Alternate Function register to select the LED function.
.
Table 30. LED Drive Enable (LEDEN) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W F82H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
BITS FIELD RESET R/W ADDR
LEDEN[7:0]
LEDEN[7:0]--LED Drive Enable These bits determine which Port C pins are connected to an internal current sink.
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0 = Tristate the Port C pin. 1= Enable controlled current sink on the Port C pin.
LED Drive Level High Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 31). These two bits select between four programmable drive levels. Each pin is individually programmable.
Table 31. LED Drive Level High Register (LEDLVLH) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W F83H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
LEDLVLH[7:0]
LEDLVLH[7:0]--LED Level High Bit {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin. 00 = 3 mA 01= 7 mA 10= 13 mA 11= 20 mA
LED Drive Level Low Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 32). These two bits select between four programmable drive levels. Each pin is individually programmable.
Table 32. LED Drive Level Low Register (LEDLVLL) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W F84H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
LEDLVLL[7:0]
LEDLVLH[7:0]--LED Level High Bit {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.
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00 = 3 mA 01 = 7 mA 10 = 13 mA 11 = 20 mA
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Interrupt Controller
Overview
The interrupt controller on the Z8 Encore! XP(R) 4K Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following:
* * * *
20 unique interrupt vectors: - 12 GPIO port pin interrupt sources (two are shared) - 10 on-chip peripheral interrupt sources (two are shared) Flexible GPIO interrupts - Eight selectable rising and falling edge GPIO interrupts - Four dual-edge interrupts Three levels of individually programmable interrupt priority Watch-Dog Timer and LVD can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control information between the CPU and the interrupting peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Manual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 33 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address. Note: Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is unavailable on devices not containing an ADC.
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Table 33. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H 0004H 003AH 003CH 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H Reset (not an interrupt) Watch-Dog Timer (see Watch-Dog Timer chapter) Primary Oscillator Fail Trap (not an interrupt) Watchdog Oscillator Fail Trap (not an interrupt) Illegal Instruction Trap (not an interrupt) Reserved Timer 1 Timer 0 UART 0 receiver UART 0 transmitter Reserved Reserved ADC Port A7, selectable rising or falling input edge or LVD (see the chapter Reset,
STOP Mode Recovery and Low Voltage Detection on page 20)
Port A6, selectable rising or falling input edge or Comparator Output Port A5, selectable rising or falling input edge Port A4, selectable rising or falling input edge Port A3 or Port D3, selectable rising or falling input edge Port A2 or Port D2, selectable rising or falling input edge Port A1, selectable rising or falling input edge Port A0, selectable rising or falling input edge Reserved Reserved Reserved Reserved Port C3, both input edges Port C2, both input edges Port C1, both input edges
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Table 33. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source Lowest 0036H 0038H Port C0, both input edges Reserved
Architecture
Figure 8 illustrates the interrupt controller block diagram.
Port Interrupts Interrupt Request Latches and Control
High Priority Vector Priority Mux IRQ Request
Medium Priority
Internal Interrupts
Low Priority
Figure 8.Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions:
* *
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Execution of an EI (Enable Interrupt) instruction Execution of an IRET (Return from Interrupt) instruction
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* * * * * * * * *
Writing a 1 to the IRQE bit in the Interrupt Control register Execution of a DI (Disable Interrupt) instruction eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller Writing a 0 to the IRQE bit in the Interrupt Control register Reset Execution of a Trap instruction Illegal Instruction Trap Primary Oscillator Fail Trap Watch-Dog Oscillator Fail Trap
Interrupts are globally disabled by any of the following actions:
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for example), the interrupt priority is assigned from highest to lowest as specified in Table 33 on page 51. Level 3 interrupts are always assigned higher priority than Level 2 interrupts which, in turn, always are assigned higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 33, above. Reset, Watch-Dog Timer interrupt (if enabled), Primary Oscillator Fail Trap, Watchdog Oscillator Fail Trap, and Illegal Instruction Trap always have highest (level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request. Caution: The following coding style that clears bits in the Interrupt Request registers is NOT recommended. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0
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Caution:
To avoid missing interrupts, use the following coding style to clear bits in the Interrupt Request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is automatically cleared to 0. Caution: The following coding style used to generate software interrupts by setting bits in the Interrupt Request registers is NOT recommended. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 Caution: To avoid missing interrupts, use the following coding style to set bits in the Interrupt Request registers: Good coding style that avoids lost interrupt requests: ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
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interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending.
Table 34. Interrupt Request 0 Register (IRQ0) BITS FIELD RESET R/W ADDR 7 Reserved 0 R/W 6 T1I 0 R/W 5 T0I 0 R/W 4 U0RXI 0 R/W FC0H 3 U0TXI 0 R/W 2 Reserved 0 R/W 1 Reserved 0 R/W 0 ADCI 0 R/W
Reserved--Must be 0. T1I--Timer 1 Interrupt Request 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. T0I--Timer 0 Interrupt Request 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. U0RXI--UART 0 Receiver Interrupt Request 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. U0TXI--UART 0 Transmitter Interrupt Request 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. ADCI--ADC Interrupt Request 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 35) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.
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Table 35. Interrupt Request 1 Register (IRQ1) BITS FIELD RESET R/W ADDR 7 PA7VI 0 R/W 6 PA6CI 0 R/W 5 PA5I 0 R/W 4 PA4I 0 R/W FC3H 3 PA3I 0 R/W 2 PA2I 0 R/W 1 PA1I 0 R/W 0 PA0I 0 R/W
PA7VI--Port A7 or LVD Interrupt Request 0 = No interrupt request is pending for GPIO Port A or LVD. 1 = An interrupt request from GPIO Port A or LVD. PA6CI--Port A6 or Comparator Interrupt Request 0 = No interrupt request is pending for GPIO Port A or Comparator. 1 = An interrupt request from GPIO Port A or Comparator. PAxI--Port A Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port A pin x. 1 = An interrupt request from GPIO Port A pin x is awaiting service. where x indicates the specific GPIO Port pin number (0-5).
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 36) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2 register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 2 Register (IRQ2) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 7 6 Reserved 0 R/W 0 R/W FC6H 5 4 3 PC3I 0 R/W 2 PC2I 0 R/W 1 PC1I 0 R/W 0 PC0I 0 R/W
Reserved--Must be 0. PCxI--Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0-3).
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IRQ0 Enable High and Low Bit Registers
Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit registers (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt Request 0 register.
Table 37. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Medium High
where x indicates the register bits from 0-7.
Table 38. IRQ0 Enable High Bit Register (IRQ0ENH) BITS FIELD RESET R/W ADDR 7 Reserved 0 R/W 6 T1ENH 0 R/W 5 T0ENH 0 R/W 4 U0RENH 0 R/W FC1H 3 U0TENH 0 R/W 2 Reserved 0 R/W 1 Reserved 0 R/W 0 ADCENH 0 R/W
Reserved--Must be 0. T1ENH--Timer 1 Interrupt Request Enable High Bit T0ENH--Timer 0 Interrupt Request Enable High Bit U0RENH--UART 0 Receive Interrupt Request Enable High Bit U0TENH--UART 0 Transmit Interrupt Request Enable High Bit ADCENH--ADC Interrupt Request Enable High Bit
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL) BITS FIELD RESET R/W ADDR 7 Reserved 0 R 6 T1ENL 0 R/W 5 T0ENL 0 R/W 4 U0RENL 0 R/W FC2H 3 U0TENL 0 R/W 2 Reserved 0 R 1 Reserved 0 R 0 ADCENL 0 R/W
Reserved--Must be 0.
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T1ENL--Timer 1 Interrupt Request Enable Low Bit T0ENL--Timer 0 Interrupt Request Enable Low Bit U0RENL--UART 0 Receive Interrupt Request Enable Low Bit U0TENL--UART 0 Transmit Interrupt Request Enable Low Bit ADCENL--ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 40 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit registers (Tables 41 and 42) form a priority encoded enabling for interrupts in the Interrupt Request 1 register.
Table 40. IRQ1 Enable and Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Medium High
where x indicates the register bits from 0-7.
Table 41. IRQ1 Enable High Bit Register (IRQ1ENH) BITS FIELD RESET R/W ADDR 7 0 R/W 6 0 R/W 5 PA5ENH 0 R/W 4 PA4ENH 0 R/W FC4H 3 PA3ENH 0 R/W 2 PA2ENH 0 R/W 1 PA1ENH 0 R/W 0 PA0ENH 0 R/W
PA7VENH PA6CENH
PA7VENH--Port A Bit[7] or LVD Interrupt Request Enable High Bit PA6CENH--Port A Bit[7] or Comparator Interrupt Request Enable High Bit PAxENH--Port A Bit[x] Interrupt Request Enable High Bit Refer to the Shared Interrupt Select (IRQSS) register for selection of either the LVD or the comparator as the interrupt source.
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Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL) BITS FIELD RESET R/W ADDR 7 0 R/W 6 0 R/W 5 PA5ENL 0 R/W 4 PA4ENL 0 R/W FC5H 3 PA3ENL 0 R/W 2 PA2ENL 0 R/W 1 PA1ENL 0 R/W 0 PA0ENL 0 R/W
PA7VENL PA6CENL
PA7VENL--Port A Bit[7] or LVD Interrupt Request Enable Low Bit PA6CENL--Port A Bit[6] or Comparator Interrupt Request Enable Low Bit PAxENL--Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
Table 43 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit registers (Tables 44 and 45) form a priority encoded enabling for interrupts in the Interrupt Request 2 register.
Table 43. IRQ2 Enable and Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Medium High
where x indicates the register bits from 0-7.
Table 44. IRQ2 Enable High Bit Register (IRQ2ENH) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 7 6 Reserved 0 R/W 0 R/W FC7H 5 4 3 C3ENH 0 R/W 2 C2ENH 0 R/W 1 C1ENH 0 R/W 0 C0ENH 0 R/W
Reserved--Must be 0. C3ENH--Port C3 Interrupt Request Enable High Bit C2ENH--Port C2 Interrupt Request Enable High Bit
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C1ENH--Port C1 Interrupt Request Enable High Bit C0ENH--Port C0 Interrupt Request Enable High Bit
Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 7 6 5 Reserved 0 R/W 0 R/W FC8H 4 3 C3ENL 0 R/W 2 C2ENL 0 R/W 1 C1ENL 0 R/W 0 C0ENL 0 R/W
Reserved--Must be 0. C3ENL--Port C3 Interrupt Request Enable Low Bit C2ENL--Port C2 Interrupt Request Enable Low Bit C1ENL--Port C1 Interrupt Request Enable Low Bit C0ENL--Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 46) determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A or Port D input pin.
Table 46. Interrupt Edge Select Register (IRQES) BITS FIELD RESET R/W ADDR 7 IES7 0 R/W 6 IES6 0 R/W 5 IES5 0 R/W 4 IES4 0 R/W FCDH 3 IES3 0 R/W 2 IES2 0 R/W 1 IES1 0 R/W 0 IES0 0 R/W
IESx--Interrupt Edge Select x 0 = An interrupt request is generated on the falling edge of the PAx input or PDx. 1 = An interrupt request is generated on the rising edge of the PAx input PDx. where x indicates the specific GPIO Port pin number (0 through 7).
Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) register (Table 47) determines the source of the PADxS interrupts. The Shared Interrupt Select register selects between Port A and alternate sources for the individual interrupts.
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Because these shared interrupts are edge-triggered, it is possible to generate an interrupt just by switching from one shared source to another. For this reason, an interrupt must be disabled before switching between sources.
Table 47. Shared Interrupt Select Register (IRQSS) BITS FIELD RESET R/W ADDR 7 PA7VS 0 R/W 6 PA6CS 0 R/W 0 R/W 0 R/W FCEH 0 R/W 5 4 3 Reserved 0 R/W 0 R/W 0 R/W 2 1 0
PA7VS--PA7/LVD Selection 0 = PA7 is used for the interrupt for PA7VS interrupt request. 1 = The LVD is used for the interrupt for PA7VS interrupt request. PA6CS--PA6/Comparator Selection 0 = PA6 is used for the interrupt for PA6CS interrupt request. 1 = The Comparator is used for the interrupt for PA6CS interrupt request. Reserved--Must be 0.
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 48) contains the master enable bit for all interrupts.
Table 48. Interrupt Control Register (IRQCTL) BITS FIELD RESET R/W ADDR 7 IRQE 0 R/W 0 R 0 R 0 R FCFH 6 5 4 3 Reserved 0 R 0 R 0 R 0 R 2 1 0
IRQE--Interrupt Request Enable This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return) instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct register write of a 0 to this bit. 0 = Interrupts are disabled. 1 = Interrupts are enabled. Reserved--Must be 0.
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Timers
Overview
These Z8 Encore! XP(R) 4K Series products contain two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The timers' features include:
* * * * * * *
16-bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. Timer output pin Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generator of the UART (if unused) may also provide basic timing functionality. Refer to chapter UART on page 89 for information about using the Baud Rate Generator as an additional timer.
Architecture
Figure 9 illustrates the architecture of the timers.
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Timer Block Data Bus Block Control Timer Control
Compare
16-Bit Reload Register
System Clock Timer Input Gate Input Capture Input
16-Bit Counter with Prescaler Compare
Interrupt, PWM, and Timer Output Control
Timer Interrupt Timer Output Timer Output Complement
16-Bit PWM/Compare
Figure 9.Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128. If the Timer reaches FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops counting. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
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it is appropriate to have the Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT mode. After starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for ONE-SHOT mode. - Set the prescale value. - Set the initial output level (High or Low) if using the Timer Output alternate function. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: ( Reload Value - Start Value ) x Prescale One-Shot Mode Time-Out Period (s) = -----------------------------------------------------------------------------------------------System Clock Frequency (Hz) CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CONTINUOUS mode. - Set the prescale value.
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If using the Timer Output alternate function, set the initial output level (High or Low).
2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This action only affects the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of
0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin (if using the Timer Output function) for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation:
Reload Value x Prescale Continuous Mode Time-Out Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT mode equation to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. Caution: The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the input signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for COUNTER mode
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Select either the rising edge or falling edge of the Timer Input signal for the count. This selection also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is not required to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. In COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: Counter Mode Timer Input Transitions = Current Count Value - Start Value COMPARATOR COUNTER Mode In COMPARATOR COUNTER mode, the timer counts input transitions from the analog comparator output. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. In COMPARATOR COUNTER mode, the prescaler is disabled. Caution: The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. After reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COMPARATOR COUNTER mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer
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Configure the timer for COMPARATOR COUNTER mode Select either the rising edge or falling edge of the comparator output signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is not required to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This action only affects the first pass in COMPARATOR COUNTER mode. After the first timer Reload in COMPARATOR COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COMPARATOR COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer. In COMPARATOR COUNTER mode, the number of comparator output transitions since the timer start is given by the following equation: Comparator Output Transitions = Current Count Value - Start Value PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H.
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The steps for configuring a timer for PWM SINGLE OUTPUT mode and initiating the PWM operation are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for PWM SINGLE OUTPUT mode. - Set the prescale value. - Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. 5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is represented by the following equation: Reload Value x Prescale PWM Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented by: Reload Value - PWM Value PWM Output High Time Ratio (%) = ----------------------------------------------------------------------- x 100 Reload Value If TPOL is set to 1, the ratio of the PWM output High time to the total period is represented by: PWM Value PWM Output High Time Ratio (%) = --------------------------------- x 100 Reload Value
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PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT mode, the timer outputs a Pulse-Width Modulated (PWM) output signal pair (basic PWM signal and its complement) through two GPIO Port pins. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The timer also generates a second PWM output signal Timer Output Complement. The Timer Output Complement is the complement of the Timer Output PWM signal. A programmable deadband delay can be configured to time delay (0 to 128 system clock cycles) PWM output transitions on these two pins from a low to a high (inactive to active). This ensures a time gap between the deassertion of one PWM output to the assertion of its complement. The steps for configuring a timer for PWM DUAL OUTPUT mode and initiating the PWM operation are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for PWM DUAL OUTPUT mode by writing the TMODE bits in the TxCTL1 register and theTMODEHI bit in TxCTL0 register. - Set the prescale value. - Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the PWM Control register to set the PWM dead band delay value. The deadband delay must be less than the duration of the positive phase of the PWM signal (as defined by the PWM high and low byte registers). It must also be less than the
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duration of the negative phase of the PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). 5. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. 6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin for the Timer Output and Timer Output Complement alternate functions. The Timer Output Complement function is shared with the Timer Input function for both timers. Setting the timer mode to Dual PWM automatically switches the function from Timer In to Timer Out Complement. 8. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is represented by the following equation: Reload Value x Prescale PWM Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation determines the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented by: Reload Value - PWM Value PWM Output High Time Ratio (%) = ----------------------------------------------------------------------- x 100 Reload Value If TPOL is set to 1, the ratio of the PWM output High time to the total period is represented by: PWM Value PWM Output High Time Ratio (%) = --------------------------------- x 100 Reload Value CAPTURE Mode In CAPTURE mode, the current timer count value is recorded when the appropriate external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is because of an input capture event. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an
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interrupt and continues counting. The INPCAP bit in TxCTL0 register clears indicating the timer interrupt is not because of an input capture event. The steps for configuring a timer for CAPTURE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CAPTURE mode. - Set the prescale value. - Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these registers allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. 5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. 6. Configure the associated GPIO port pin for the Timer Input alternate function. 7. Write to the Timer Control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value - Start Value ) x Prescale Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------System Clock Frequency (Hz) CAPTURE RESTART Mode In CAPTURE RESTART mode, the current timer count value is recorded when the acceptable external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is because of an input capture event.
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If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is cleared to indicate the timer interrupt is not caused by an input capture event. The steps for configuring a timer for CAPTURE RESTART mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CAPTURE RESTART mode by writing the TMODE bits in the TxCTL1 register and the TMODEHI bit in TxCTL0 register. - Set the prescale value. - Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. 5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. 6. Configure the associated GPIO port pin for the Timer Input alternate function. 7. Write to the Timer Control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value - Start Value ) x Prescale Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------System Clock Frequency (Hz) COMPARE Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
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the Timer Output pin changes state (from Low to High or from High to Low) upon Compare. If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for COMPARE mode. - Set the prescale value. - Set the initial logic level (High or Low) for the Timer Output alternate function, if appropriate. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In Compare mode, the system clock always provides the timer input. The Compare time can be calculated by the following equation: ( Compare Value - Start Value ) x Prescale Compare Mode Time (s) = -----------------------------------------------------------------------------------------------------System Clock Frequency (Hz) GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. The steps for configuring a timer for GATED mode and initiating the count are as follows:
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1. Write to the Timer Control register to: - Disable the timer - Configure the timer for GATED mode. - Set the prescale value. 2. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input deassertion and reload events. If appropriate, configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting TICONFIG field of the TxCTL0 register. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control register to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent acceptable transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is caused by an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is cleared to indicate the timer interrupt is not because of an input capture event. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CAPTURE/COMPARE mode. - Set the prescale value.
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Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control register to enable the timer. 7. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event can be calculated using the following equation:
Capture Elapsed Time (s) = ( Capture Value - Start Value ) x Prescale --------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte register is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter.
Timer Pin Signal Operation
Timer Output is a GPIO Port pin alternate function. The Timer Output is toggled every time the counter is reloaded. The Timer Input can be used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO Alternate Function Registers, this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT mode. For this mode, there is no timer input available.
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Timer Control Register Definitions
Timer 0-1 High and Low Byte Registers
The Timer 0-1 High and Low Byte (TxH and TxL) registers (Tables 49 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TxL always returns this temporary register when the timers are enabled. When the timer is disabled, reads from TxL read the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for write operations, so simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value.
Table 49. Timer 0-1 High Byte Register (TxH) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 TH 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
F00H, F08H Table 50. Timer 0-1 Low Byte Register (TxL)
BITS FIELD RESET R/W ADDR
7 0 R/W
6 0 R/W
5 0 R/W
4 TL 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 1 R/W
F01H, F09H
TH and TL--Timer High and Low Bytes These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-1 Reload High and Low Byte (TxRH and TxRL) registers (Tables 51 and 41) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte register are stored in a temporary holding register. When a write to the Timer Reload Low Byte register occurs, the temporary holding register value is written to the Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer
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Reload value. In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit Compare value.
Table 51. Timer 0-1 Reload High Byte Register (TxRH) BITS FIELD RESET R/W ADDR 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 TRH 1 R/W 1 R/W 1 R/W 1 R/W 3 2 1 0
F02H, F0AH Table 52. Timer 0-1 Reload Low Byte Register (TxRL)
BITS FIELD RESET R/W ADDR
7 1 R/W
6 1 R/W
5 1 R/W
4 TRL 1 R/W
3 1 R/W
2 1 R/W
1 1 R/W
0 1 R/W
F03H, F0BH
TRH and TRL--Timer Reload Register High and Low These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count value which initiates a timer reload to 0001H. In Compare mode, these two bytes form the 16-bit Compare value.
Timer 0-1 PWM High and Low Byte Registers
The Timer 0-1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 53 and Table 54) control Pulse-Width Modulator (PWM) operations. These registers also store the Capture values for the CAPTURE and CAPTURE/COMPARE modes.
Table 53. Timer 0-1 PWM High Byte Register (TxPWMH) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 PWMH 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
F04H, F0CH
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Table 54. Timer 0-1 PWM Low Byte Register (TxPWML) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 PWML 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
F05H, F0DH
PWMH and PWML--Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1) register. The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operating in Capture or Capture/Compare modes.
Timer 0-1 Control Registers
Time 0-1 Control Register 0 The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) determine the timer operating mode. It also includes a programmable PWM deadband delay, two bits to configure timer interrupt definition, and a status bit to identify if the most recent timer interrupt is caused by an input capture event.
Table 55. Timer 0-1 Control Register 0 (TxCTL0) BITS FIELD RESET R/W ADDR 7 TMODEHI 0 R/W 6 TICONFIG 0 R/W 0 R/W 5 4 Reserved 0 R/W 0 R/W 3 2 PWMD 0 R/W 0 R/W 1 0 INPCAP 0 R
F06H, F0EH
TMODEHI--Timer Mode High Bit This bit along with the TMODE field in TxCTL1 register determines the operating mode of the timer. This is the most significant bit of the Timer mode selection value. See the TxCTL1 register description for details of the full timer mode decoding. TICONFIG--Timer Interrupt Configuration This field configures timer interrupt definition.
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0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events 10 = Timer Interrupt only on defined Input Capture/Deassertion Events 11 = Timer Interrupt only on defined Reload/Compare Events Reserved--Must be 0. PWMD--PWM Delay value This field is a programmable delay to control the number of system clock cycles delay before the Timer Output and the Timer Output Complement are forced to their active state. 000 = No delay 001 = 2 cycles delay 010 = 4 cycles delay 011 = 8 cycles delay 100 = 16 cycles delay 101 = 32 cycles delay 110 = 64 cycles delay 111 = 128 cycles delay INPCAP--Input Capture Event This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event. 0 = Previous timer interrupt is not a result of Timer Input Capture Event 1 = Previous timer interrupt is a result of Timer Input Capture Event Timer 0-1 Control Register 1 The Timer 0-1 Control (TxCTL1) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode.
Table 56. Timer 0-1 Control Register 1 (TxCTL1) BITS FIELD RESET R/W ADDR 7 TEN 0 R/W 6 TPOL 0 R/W 0 R/W 5 4 PRES 0 R/W 0 R/W 0 R/W 3 2 1 TMODE 0 R/W 0 R/W 0
F07H, F0FH
TEN--Timer Enable 0 = Timer is disabled. 1 = Timer enabled to count. TPOL--Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit.
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When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM SINGLE OUTPUT mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal. PWM DUAL OUTPUT mode 0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output Complement is forced Low (0) upon PWM count match and forced High (1) upon Reload. The PWMD field in TxCTL0 register is a programmable delay to control the
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number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High (1). 1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload.When enabled, the Timer Output Complement is forced High (1) upon PWM count match and forced Low (0) upon Reload. The PWMD field in TxCTL0 register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low (0). CAPTURE RESTART mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARATOR COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. Also: 0 = Count is captured on the rising edge of the comparator output. 1 = Count is captured on the falling edge of the comparator output. Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT will change to whatever state the TPOL bit is in.The timer does not need to be enabled for that to happen. Also, the Port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. PRES--Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This reset ensures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE--Timer mode This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the Timer mode selection value.
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0000 = ONE-SHOT mode 0001 = CONTINUOUS mode 0010 = COUNTER mode 0011 = PWM SINGLE OUTPUT mode 0100 = CAPTURE mode 0101 = COMPARE mode 0110 = GATED mode 0111 = CAPTURE/COMPARE mode 1000 = PWM DUAL OUTPUT mode 1001 = CAPTURE RESTART mode 1010 = COMPARATOR COUNTER mode
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Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) protects against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore! XP(R) 4K Series devices into unsuitable operating states. The Watch-Dog Timer includes the following features:
* * * Operation
On-chip RC oscillator A selectable time-out response: reset or interrupt 24-bit programmable time-out value
The Watch-Dog Timer (WDT) is a one-shot timer that resets or interrupts the Z8 Encore! XP(R) 4K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses a dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer operates in only two modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash Option Bit. The WDT_AO bit forces the Watch-Dog Timer to operate immediately upon reset, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is described by the following equation:
WDT Reload Value WDT Time-out Period (ms) = ------------------------------------------------10
where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10KHz. The Watch-Dog Timer cannot be refreshed after it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 57 provides information about approximate time-out delays for the minimum and maximum WDT reload values.
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Table 57. Watch-Dog Timer Approximate Time-Out Delays Approximate Time-Out Delay (with 10KHz typical WDT oscillator frequency) Typical 400 s 28 minutes Description Minimum time-out delay Maximum time-out delay
WDT Reload Value (Hex) 000004 FFFFFF
WDT Reload Value (Decimal) 4 16,777,215
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog Timer counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload registers. Counting resumes following the reload operation. When the Z8 Encore! XP(R) 4K Series devices are operating in DEBUG Mode (using the on-chip debugger), the Watch-Dog Timer is continuously refreshed to prevent any WatchDog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the Watch-Dog Timer generates either an interrupt or a system reset. The WDT_RES Flash Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the chapter Flash Option Bits on page 148 for information regarding programming of the WDT_RES Flash Option Bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Status (RSTSTAT) register (see page 27). If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watch-Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The WatchDog Timer counter is not automatically returned to its Reload Value. The Reset Status (RSTSTAT) Register must be read before clearing the WDT interrupt. This read clears the WDT timeout flag and prevents further WDT interrupts from immediately occurring.
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WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP(R) 4K Series devices are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) register are set to 1 following a WDT time-out in STOP mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on page 20 for more information about STOP Mode Recovery. If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. WDT Reset in NORMAL Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT) register is set to 1. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on page 20 for more information about system reset. WDT Reset in STOP Mode If configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) register are set to 1 following WDT time-out in STOP mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on page 20 for more information.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The following sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access. 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU). 4. Write the Watch-Dog Timer Reload High Byte register (WDTH). 5. Write the Watch-Dog Timer Reload Low Byte register (WDTL).
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All three Watch-Dog Timer Reload registers must be written in the order just listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.
Watch-Dog Timer Calibration
Due to its extremely low operating current, the Watch-Dog Timer oscillator is somewhat inaccurate. This variation can be corrected using the calibration data stored in the Flash Information Page (see Tables 98 and 99 on page 158). Loading these values into the Watch-Dog Timer Reload Registers will result in a one-second timeout at room temperature and 3.3V supply voltage. Timeouts other than one second may be obtained by scaling the calibration values up or down as required. Note that the Watch-Dog Timer accuracy will still degrade as temperature and supply voltage vary. See Table 136, Watch-Dog Timer Electrical Characteristics and Timing on page 220 for details.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register is a write-only control register. Writing the 55H, AAH unlock sequence to the WDTCTL register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. This register address is shared with the read-only Reset Status Register.
Table 58. Watch-Dog Timer Control Register (WDTCTL) BITS FIELD RESET R/W ADDR X W X W X W 7 6 5 4 X W FF0H 3 X W 2 X W 1 X W 0 X W
WDTUNLK
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WDTUNLK--Watch-Dog Timer Unlock The user software must write the correct unlocking sequence to this register before it is allowed to modify the contents of the watch-dog timer reload registers.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers (Tables 59 through 61) form the 24-bit reload value that is loaded into the WatchDog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate Reload Value. Reading from these registers returns the current Watch-Dog Timer count value. Caution: The 24-bit WDT Reload Value must not be set to a value less than 000004H.
Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU) BITS FIELD RESET R/W ADDR 7 6 5 4 WDTU FFH R/W* FF1H 3 2 1 0
R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.
WDTU--WDT Reload Upper Byte Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 60. Watch-Dog Timer Reload High Byte Register (WDTH) BITS FIELD RESET R/W ADDR 7 6 5 4 WDTH FFH R/W* FF2H 3 2 1 0
R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.
WDTH--WDT Reload High Byte Middle byte, Bits[15:8], of the 24-bit WDT reload value.
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Table 61. Watch-Dog Timer Reload Low Byte Register (WDTL) BITS FIELD RESET R/W ADDR 7 6 5 4 WDTL FFH R/W* FF3H 3 2 1 0
R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.
WDTL--WDT Reload Low Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
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UART
Overview
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include:
* * * * * * * * * *
Architecture
8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking Option of one or two STOP bits Separate transmit and receive interrupts Framing, parity, overrun and break detection Separate transmit and receive enables 16-bit baud rate generator (BRG) Selectable MULTIPROCESSOR (9-bit) mode with three configurable interrupt schemes Baud rate generator (BRG) can be configured and used as a basic 16-bit timer Driver enable (DE) output for external bus transceivers
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART's transmitter and receiver function independently, but employ the same baud rate and data format. Figure 10 illustrates the UART architecture.
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Parity Checker Receiver Control with Address Compare RXD Receive Shifter
Receive Data Register
Control Registers
System Bus
Transmit Data Register
Status Register
Baud Rate Generator
TXD
Transmit Shift Register Transmitter Control Parity Generator
CTS DE
Figure 10.UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit can be added to the data stream. Each character begins with an active Low START bit and ends with either 1 or 2 active High STOP bits. Figures 11 and 12 illustrates the asynchronous data format employed by the UART without parity and with parity, respectively.
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1 0
Idle State of Line Start
Data Field lsb Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 msb Bit7
Stop Bit(s)
1 2
Figure 11.UART Asynchronous Data Format without Parity
1 0
Idle State of Line Start
Data Field lsb Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 msb Bit7 Parity
Stop Bit(s)
1 2
Figure 12.UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled method of operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the required baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Write to the UART Control 1 register, if MULTIPROCESSOR mode is appropriate, to enable MULTIPROCESSOR (9-bit) mode functions. 4. Set the Multiprocessor Mode Select (MPEN) bit to enable MULTIPROCESSOR mode. 5. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - Set the parity enable bit (PEN), if parity is appropriate and MULTIPROCESSOR mode is not enabled, and select either even or odd parity (PSEL). - Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin.
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6. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. 7. Write the UART Control 1 register to select the outgoing address bit. 8. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 9. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate and MULTIPROCESSOR mode is enabled,. 11. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interruptdriven data transmission: 1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority. 5. Write to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode functions, if MULTIPROCESSOR mode is appropriate. 6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR mode. 7. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - Enable parity, if appropriate and if MULTIPROCESSOR mode is not enabled, and select either even or odd parity. - Set or clear CTSE to enable or disable control from the remote receiver using the CTS pin. 8. Execute an EI instruction to enable interrupts.
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The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 register to select the multiprocessor bit for the byte to be transmitted: Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 2. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow these steps to configure the UART for polled data reception: 5. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream. 6. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 7. Write to the UART Control 1 register to enable MULTIPROCESSOR mode functions, if appropriate. 8. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if appropriate and if Multiprocessor mode is not enabled, and select either even or odd parity. 9. Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 5. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 10. Read data from the UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR mode bits MPMD[1:0]. 11. Return to Step 4 to receive additional data.
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Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow these steps to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority. 5. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if appropriate. - Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR mode. - Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address matching scheme. - Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore!(R) devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic MULTIPROCESSOR modes only). 8. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if appropriate and if multiprocessor mode is not enabled, and select either even or odd parity. 9. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Checks the UART Status 0 register to determine the source of the interrupt - error, break, or received data. 2. Reads the data from the UART Receive Data register if the interrupt was because of data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR mode bits MPMD[1:0]. 3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.
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4. Executes the IRET instruction to return from the interrupt-service routine and await more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins. For multiple character transmissions, this action is typically performed during Stop Bit transmission. If CTS deasserts in the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common UART bus. In MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immediately following the 8-bits of data and immediately preceding the Stop bit(s) as illustrated in Figure 13. The character format is:
Data Field lsb Start 0 1 2 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 msb Bit7 MP Stop Bit(s)
1
Idle State of Line
Figure 13.UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers provide MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address matching scheme is enabled, the UART Address Compare register holds the network address of the device. MULTIPROCESSOR (9-bit) Mode Receive Interrupts When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data directed to other
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devices on the multi-node network. The following three MULTIPROCESSOR modes are available in hardware:
* * *
Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all multiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. Each new incoming byte interrupts the CPU. The software is responsible for determining the end of the frame. It checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART's address, MPMD[0] must be set to 1 causing the UART interrupts to go inactive until the next address byte. If the new frame's address matches the UART's, the data in the new frame is processed as well. The second scheme requires the following: set MPMD[1:0] to 10B and write the UART's address into the UART Address Compare Register. This mode introduces additional hardware control, interrupting only on frames that match the UART's address. When an incoming address byte does not match the UART's address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts now occur on each succesive data byte. When the first data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted. All successive data bytes have NEWFRM=0. When the next address byte occurs, the hardware compares it to the UART's address. If there is a match, the interrupts continues and the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART's address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame remains accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 14. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal
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asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after the final Stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows the current character. In the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is not deasserted between characters. The Depol bit in the UART Control Register 1 sets the polarity of the Driver Enable signal.
1 DE 0 Data Field lsb Start 0 1 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 msb Bit7 Parity Stop Bit
1
Idle State of Line
Figure 14.UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1 2 ------------------------------------ DE to Start Bit Setup Time (s) ------------------------------------ Baud Rate (Hz) Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out. The Transmit Data register can now be written with the next character to send. This action provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the TDRE bit to 0.
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Receiver Interrupts The receiver generates an interrupt when any of the following occurs:
*
A data byte is received and is available in the UART Receive Data register. This interrupt can be disabled independently of the other receiver interrupt sources. The received data interrupt occurs after the receive character has been received and placed in the Receive Data register. To avoid an overrun error, software must respond to this received data available condition before the next character is completely received.
Note:
In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte.
* * *
A break is received An overrun is detected A data framing error is detected
UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and must be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 15 illustrates the recommended procedure for use in UART receiver interrupt service routines.
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Receiver Ready
Receiver Interrupt
Read Status
No Errors?
Yes Read Data which clears RDA bit and resets error bits
Read Data
Discard Data
Figure 15.UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts If the baud rate generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
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(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated using the following equation:
System Clock Frequency (Hz) UART Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0. 2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the UART Control 1 register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ]
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/ Decoders. For more information about the infrared operation, refer to the Infrared Encoder/Decoder chapter on page 109.
UART Transmit Data Register
Data bytes written to the UART Transmit Data (UxTXD) register (Table 62) are shifted out on the TXDx pin. The Write-only UART Transmit Data register shares a Register File address with the read-only UART Receive Data register.
Table 62. UART Transmit Data Register (U0TXD) BITS FIELD RESET R/W ADDR X W X W X W X W F40H 7 6 5 4 TXD X W X W X W X W 3 2 1 0
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TXD--Transmit Data UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data (UxRXD) register (Table 63). The read-only UART Receive Data register shares a Register File address with the Write-only UART Transmit Data register.
Table 63. UART Receive Data Register (U0RXD) BITS FIELD RESET R/W ADDR X R X R X R X R F40H 7 6 5 4 RXD X R X R X R X R 3 2 1 0
RXD--Receive Data UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 (UxSTAT0) and Status 1(UxSTAT1) registers (Tables 64 and 65) identify the current UART operating configuration and status.
Table 64. UART Status 0 Register (U0STAT0) BITS FIELD RESET R/W ADDR 7 RDA 0 R 6 PE 0 R 5 OE 0 R 4 FE 0 R F41H 3 BRKD 0 R 2 TDRE 1 R 1 TXE 1 R 0 CTS X R
RDA--Receive Data Available This bit indicates that the UART Receive Data register has received data. Reading the UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. PE--Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data register clears this bit.
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0 = No parity error has occurred. 1 = A parity error has occurred. OE--Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE--Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD--Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE--Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmitted. TXE--Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is finished. 0 = Data is currently transmitting. 1 = Transmission is complete. CTS--CTS signal When this bit is read it returns the level of the CTS signal. This signal is active Low.
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UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 65. UART Status 1 Register (U0STAT1) BITS FIELD RESET R/W ADDR 0 R 0 R 0 R 7 6 5 Reserved 0 R F44H 0 R/W 0 R/W 4 3 2 1 NEWFRM 0 R 0 MPRX 0 R
Reserved--Must be 0. NEWFRM--Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. MPRX--Multiprocessor Receive Returns the value of the most recent multiprocessor bit received. Reading from the UART Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers (Tables 66 and 67) configure the properties of the UART's transmit and receive operations. The UART Control registers must not be written while the UART is enabled.
Table 66. UART Control 0 Register (U0CTL0) BITS FIELD RESET R/W ADDR 7 TEN 0 R/W 6 REN 0 R/W 5 CTSE 0 R/W 4 PEN 0 R/W F42H 3 PSEL 0 R/W 2 SBRK 0 R/W 1 STOP 0 R/W 0 LBEN 0 R/W
TEN--Transmit Enable This bit enables or disables the transmitter. The enable is also controlled by the CTS signal and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled. 0 = Transmitter disabled. 1 = Transmitter enabled.
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REN--Receive Enable This bit enables or disables the receiver. 0 = Receiver disabled. 1 = Receiver enabled. CTSE--CTS Enable 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. PEN--Parity Enable This bit enables or disables parity. Even or odd is determined by the PSEL bit. 0 = Parity is disabled. 1 = The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit. PSEL--Parity Select 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. SBRK--Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending data before setting this bit. 0 = No break is sent. 1 = Forces a break condition by setting the output of the transmitter to zero. STOP--Stop Bit Select 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. LBEN--Loop Back Enable 0 = Normal operation. 1 = All transmitted data is looped back to the receiver.
Table 67. UART Control 1 Register (U0CTL1) BITS FIELD RESET R/W ADDR 7 MPMD[1] 0 R/W 6 MPEN 0 R/W 5 MPMD[0] 0 R/W 4 MPBT 0 R/W F43H 3 DEPOL 0 R/W 2 BRGCTL 0 R/W 1 RDAIRQ 0 R/W 0 IREN 0 R/W
MPMD[1:0]--MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an
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address mismatch occurs. 11 = The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN--MULTIPROCESSOR (9-bit) Enable This bit is used to enable MULTIPROCESSOR (9-bit) mode. 0 = Disable MULTIPROCESSOR (9-bit) mode. 1 = Enable MULTIPROCESSOR (9-bit) mode. MPBT--Multiprocessor Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit is used by the receiving device to determine if the data byte contains address or data information. 0 = Send a 0 in the multiprocessor bit location of the data stream (data byte). 1 = Send a 1 in the multiprocessor bit location of the data stream (address byte). DEPOL--Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL--Baud Rate Control This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit determines whether the Baud Rate Generator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High Byte is read. RDAIRQ--Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Controller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. IREN--Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally. 1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder.
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UART Address Compare Register
The UART Address Compare (UxADDR) register stores the multi-node network address of the UART (see Table 68). When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes are compared to the value stored in the Address Compare register. Receive interrupts and RDA assertions only occur in the event of a match.
Table 68. UART Address Compare Register (U0ADDR) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W F45H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
COMP_ADDR
COMP_ADDR--Compare Address This 8-bit value is compared to incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High (UxBRH) and Low Byte (UxBRL) registers (Tables 69 and 70) combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART.
Table 69. UART Baud Rate High Byte Register (U0BRH) BITS FIELD RESET R/W ADDR 1 R/W 1 R/W 1 R/W 1 R/W F46H Table 70. UART Baud Rate Low Byte Register (U0BRL) BITS FIELD RESET R/W ADDR 1 R/W 1 R/W 1 R/W 1 R/W F47H 7 6 5 4 BRL 1 R/W 1 R/W 1 R/W 1 R/W 3 2 1 0 7 6 5 4 BRH 1 R/W 1 R/W 1 R/W 1 R/W 3 2 1 0
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The UART data rate is calculated using the following equation:
System Clock Frequency (Hz) UART Baud Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
For a given UART data rate, calculate the integer baud rate divisor value using the following equation:
System Clock Frequency (Hz) UART Baud Rate Divisor Value (BRG) = Round --------------------------------------------------------------------------- 16 x UART Data Rate (bits/s)
The baud rate error relative to the acceptable baud rate is calculated using the following equation:
Actual Data Rate - Desired Data Rate UART Baud Rate Error (%) = 100 x ------------------------------------------------------------------------------------------------ Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent. Table 71 provides information about data rate errors for popular baud rates and commonly used crystal oscillator frequencies.
Table 71. UART Baud Rates 10.0 MHz System Clock Acceptable Rate (KHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A 1 3 5 11 16 33 65 130 260 521 1042 2083 Actual Rate (KHz) N/A 625.0 208.33 125.0 56.8 39.1 18.9 9.62 4.81 2.40 1.20 0.60 0.30 Error (%) N/A 0.00 -16.67 8.51 -1.36 1.73 0.16 0.16 0.16 -0.03 -0.03 -0.03 0.2 5.5296 MHz System Clock Acceptable Rate (KHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A N/A 1 3 6 9 18 36 72 144 288 576 1152 Actual Rate (KHz) N/A N/A 345.6 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 Error (%) N/A N/A 38.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
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Table 71. UART Baud Rates (Continued) 3.579545 MHz System Clock Acceptable Rate (KHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A N/A 1 2 4 6 12 23 47 93 186 373 746 Actual Rate (KHz) N/A N/A 223.72 111.9 55.9 37.3 18.6 9.73 4.76 2.41 1.20 0.60 0.30 Error (%) N/A N/A -10.51 -2.90 -2.90 -2.90 -2.90 1.32 -0.83 0.23 0.23 -0.04 -0.04 1.8432 MHz System Clock Acceptable Rate (KHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A N/A N/A 1 2 3 6 12 24 48 96 192 384 Actual Rate (KHz) N/A N/A N/A 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 Error (%) N/A N/A N/A 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
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Infrared Encoder/Decoder
Overview
The Z8 Encore! XP(R) 4K Series products contain a fully-functional, high-performance UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an onchip UART to allow easy communication between the Z8 Encore! and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication provides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones, printers and other infrared enabled devices.
Architecture
Figure 16 illustrates the architecture of the Infrared Endec.
System Clock RxD TxD Baud Rate Clock Infrared Encoder/Decoder (Endec) RXD TXD
Infrared Transceiver RXD TXD
UART
Interrupt I/O Signal Address
Data
Figure 16.Infrared Data Communication System Block Diagram
Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver through the TXD pin. Likewise, data received from the infrared transceiver
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is passed to the Infrared Endec through the RXD pin, decoded by the Infrared Endec, and passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART's Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation:
:
System Clock Frequency (Hz) Infrared Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The UART's transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16 clock period. If the data to be transmitted is 0, the transmitter first outputs a 7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse is output to complete the full 16 clock data period. Figure 17 illustrates IrDA data transmission. When the Infrared Endec is enabled, the UART's TXD signal is internal to the Z8 Encore! XP(R) 4K Series products while the IR_TXD signal is output through the TXD pin.
16 clock period
Baud Rate Clock
UART's TXD
Start Bit = 0 3 clock pulse
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_TXD 7-clock delay
Figure 17.Infrared Data Transmission
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Receiving IrDA Data
Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART's baud rate clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives the UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 illustrates data reception. When the Infrared Endec is enabled, the UART's RXD signal is internal to the Z8 Encore! XP(R) 4K Series products while the IR_RXD signal is received through the RXD pin.
16 clock period
Baud Rate Clock Start Bit = 0 IR_RXD min. 1.4s pulse UART's RXD 8 clock delay Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
16 clock period
16 clock period
16 clock period
16 clock period
Figure 18.IrDA Data Reception
Infrared Data Reception Caution: The system clock frequency must be at least 1.0 MHz to ensure proper reception of the 1.4 s minimum width pulses allowed by the IrDA standard. Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate an input stream for the UART and to create a sampling window for detection of incoming pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream. When a falling edge in the input data stream is detected, the Endec counter is reset. When the count reaches a value of 8, the UART RXD value is updated to reflect the value of the decoded data. When the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. The window remains open until the count again reaches 8 (in other words, 24 baud clock periods since the previous pulse was detected), giving the Endec a sampling window of
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minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control registers as defined beginning on page 89. Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO Port alternate function for the corresponding pin.
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Analog-to-Digital Converter
Overview
The analog-to-digital converter (ADC) converts an analog input signal to its digital representation. The features of this sigma-delta ADC include:
* * * * * * * * * * * * Architecture
11-bit resolution in DIFFERENTIAL mode 10-bit resolution in SINGLE-ENDED mode Eight single-ended analog input sources are multiplexed with general-purpose I/O ports 9th analog input obtained from temperature sensor peripheral 11 pairs of differential inputs also multiplexed with general-purpose I/O ports Low-power operational amplifier (LPO) Interrupt on conversion complete Interrupt on sample value greater than programmable high threshold Interrupt on sample value smaller than programmable low threshold Bandgap generated internal voltage reference with two selectable levels Manual in-circuit calibration is possible employing user code (offset calibration) Factory calibrated for in-circuit error compensation
Figure 19 illustrates the major functional blocks of the ADC. An analog multiplexer network selects the ADC input from the available analog pins, ANA0 through ANA7. The input stage of the ADC allows both differential gain and buffering. The following input options are available:
* * *
Unbuffered input (SINGLE-ENDED and DIFFERENTIAL modes) Buffered input with unity gain (SINGLE-ENDED and DIFFERENTIAL modes) LPO output with full pin access to the feedback path
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2
Vrefsel
Internal Voltage Reference Generator
VREF pin
VREFEXT
Analog Input Multiplexer
ADC Data
13
Ref Input
ANA0 ANA1 ANA2 ANA3 ANA4 ANA5
13 bit Sigma-Delta ADC Analog In Analog In +
Buffer Amplifier ANAIN
4 calibration
for offset
+
Analog Input Multiplexer
ADC
IRQ
BUFFMODE
ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 Amplifier tristates when disabled
+
Low-Power Operational Amplifier
Temp Sensor
Figure 19.Analog-to-Digital Converter Block Diagram
Operation
Data Format
In both SINGLE-ENDED and DIFFERENTIAL modes, the effective output of the ADC is an 11- bit, signed, two's complement digital value. In DIFFERENTIAL mode, the ADC
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can output values across the entire 11-bit range, from -1024 to +1023. In SINGLEENDED mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. The ADC registers actually return 13 bits of data, but the two LSBs are intended for compensation use only. When the software compensation routine is performed on the 13 bit raw ADC value, two bits of resolution are lost because of a rounding error. As a result, the final value is an 11- bit number.
Automatic Powerdown
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered down. From this powerdown state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a conversion is requested by the ADC Control register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows: 1. Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate analog function. This configuration disables the digital input and output drivers. 2. Write the ADC High Threshold Register and ADC Low Threshold Register if the alarm function is required. 3. Write the ADC Control/Status Register 1 to configure the ADC - Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as well as unbuffered or buffered mode. - If the alarm function is required, set ALMHEN and/or ALMLEN. - Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is. contained in the ADC Control Register 0. 4. Write to the ADC Control Register 0 to configure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously (the ADC can be configured and enabled with the same write instruction): - Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device) - Clear CONT to 0 to select a single-shot conversion.
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- -
-
If the internal voltage reference must be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELH bit is contained in the ADC Control/Status Register 1. Set CEN to 1 to start the conversion.
5. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. 6. When the conversion is complete, the ADC control logic performs the following operations: - 13-bit two's-complement result written to {ADCD_H[7:0], ADCD_L[7:3]}. - CEN resets to 0 to indicate the conversion is complete. - If the High and Low alarms are disabled, an interrupt request is sent to the Interrupt Controller denoting conversion complete. - If the High alarm is enabled and the ADC value is higher than the alarm threshold, an interrupt is generated. - If the Low alarm is enabled and the ADC value is lower than the alarm threshold, an interrupt is generated. 7. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analogto-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each conversion. Caution: In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not immediately detected at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency. Follow these steps for setting up the ADC and initiating continuous conversion: 1. Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This action disables the digital input and output driver. 2. Write the ADC High Threshold Register and ADC Low Threshold Register if the alarm function is required.
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3. Write the ADC Control/Status Register 1 to configure the ADC - Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as well as unbuffered or buffered mode. - If the alarm function is required, set ALMHEN and/or ALMLEN. - Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is contained in the ADC Control Register 0. 4. Write to the ADC Control Register 0 to configure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: - Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device) - Set CONT to 1 to select continuous conversion. - If the internal VREF must be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. - Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELH bit is contained in ADC Control/Status Register 1. - Set CEN to 1 to start the conversions. 5. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: - CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. - An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. 6. The ADC writes a new data result every 256 system clock cycles. For each completed conversion, the ADC control logic performs the following operations: - Writes the 13-bit two's complement result to {ADCD_H[7:0], ADCD_L[7:3]}. - If the high and low alarms are disabled, sends an interrupt request to the Interrupt Controller denoting conversion complete. - If the high alarm is enabled and the ADC value is higher than the alarm threshold, generates an interrupt. - If the low alarm is enabled and the ADC value is lower than the alarm threshold, generates an interrupt. 7. To disable continuous conversion, clear the CONT bit in the ADC Control Register to 0.
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Programmable Trigger Point Alarm
The ADC contains two programmable trigger values, defined in the ADC High Threshold (ADCTHH) Register (Table 76 on page 128) and the ADC Low Threshold (ADCTLH) Register (Table 77 on page 128). Each of these values is 8 bits and is NOT a two's complement number. The alarm is intended for single-ended operation and so the alarm values reflect positive numbers only. Both thresholds have independent control and status bits. When the ADC is enabled and the ADC value exceeds the high threshold, an ADC interrupt is asserted and the high threshold status bit is set. When enabled and the ADC value is less than the low threshold, an ADC interrupt is asserted and the low threshold status bit is set. Because the alarm value is positive it is compared to the most significant 8 data bits of the ADC value, excluding the sign bit. The ADC alarm bits are compared to {ADCD_H[6:0],ADCD_L[7]}. Alternatively, the alarm value is compared to the ADC value shifted left by one bit. Negative ADC values never trigger the high alarm and always trigger the low alarm. Because the ADC output is software compensated for offset, negative (pre-compensated) values can occur in SINGLE-ENDED mode. The alarm is primarily intended for use in CONTINUOUS mode so that the CPU can determine threshold crossings without servicing interrupts for all ADC samples. If used in SINGLE-SHOT mode, the ADC will only interrupt the CPU if the single sample triggers an alarm. The alarm status bits are updated on each conversion, regardless of the alarm enable bit values. The alarm enable bits only determine whether or not an interrupt is generated.
Interrupts
The ADC is able to interrupt the CPU under three conditions:
* * *
When a conversion has been completed When the 8 Most Significant Bits of a sample exceed the programmable high threshold
ADCTHH[7:0]
When the 8 Most Significant Bits of a sample is less than the programmable low threshold
ADCTLH[7:0]
The conversion interrupt occurs when the ADC is enabled and both alarms are disabled. When either or both alarms are enabled, the conversion interrupt is disabled and only the alarm interrupts may occur. When the ADC is disabled, none of the three sources can cause an interrupt to be asserted; however, an interrupt pending when the ADC is disabled is not cleared. The three interrupt events share a common CPU interrupt. The interrupt service routine must query the ADC Control/Status (ADCCTL1) Register to determine the cause of an
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ADC interrupt. The register bits denoting ADC alarm status can only be set by hardware and are cleared by writing a 1.
Calibration and Compensation
The Z8 Encore! XP(R) 4K Series ADC is factory calibrated for offset error and gain error, with the compensation data stored in Flash memory. Alternatively, users can perform their own calibration, storing the values into Flash themselves. Thirdly, the user code can perform a manual offset calibration during DIFFERENTIAL mode operation. Factory Calibration Devices that have been factory calibrated contain 30 bytes of calibration data in the Flash option bit space. This data consists of 3 bytes for each input mode, one for offset and two for gain correction. See ZiLOG Calibration Data on page 155 for a list of input modes for which calibration data exists. User Calibration If the user has precision references available, its own external calibration can be performed using any input modes. This calibration data will take into account buffer offset and non-linearity, so it is recommended that this calibration be performed separately for each of the ADC input modes planned for use. Manual Offset Calibration When uncalibrated, the ADC has significant offset (see Table 138, Analog-to-Digital Converter Electrical Characteristics and Timing, on page 221 for details). Subsequently, manual offset calibration capability is built into the block. When the ADC Control Register 0 sets the input mode (ANAIN[2:0]) to MANUAL OFFSET CALIBRATION mode, the differential inputs to the ADC are shorted together by an internal switch. Reading the ADC value at this point produces 0 in an ideal system. The value actually read is the ADC offset. This value can be stored in non-volatile memory (Non-Volatile Data Storage on page 163) and accessed by user code to compensate for the input offset error. There is no provision for manual gain calibration. Software Compensation Procedure Using Factory Calibration Data
Overview. The value read from the ADC high and low byte registers is uncompen-
sated. The user mode software must apply gain and offset correction to this uncompensated value for maximum accuracy. The following formula yields the compensated value: ADCcomp = (ADCuncomp - OFFCAL) + ((ADCuncomp - OFFCAL)*GAINCAL)/216
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where GAINCAL is the gain calibration value, OFFCAL is the offset calibration value and ADCuncomp is the uncompensated value read from the ADC. All values are in two's complement format. Note: The offset compensation is performed first, followed by the gain compensation. One bit of resolution is lost because of rounding on both the offset and gain computations. As a result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. Also note that in the second term, the multiplication should be performed before the division by 216. Otherwise, the the second term will incorrectly evaluate to zero. Caution: Although the ADC can be used without the gain and offset compensation, it does exhibit non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8/7.
ADC Compensation Details
High efficiency assembly code that performs this compensation is available for download on www.zilog.com. The following is a bit-specific description of the ADC compensation process used by this code. The following data bit definitions are used: 0-9, a-f = bit indices in hexadecimal s = sign bit v = overflow bit - = unused Input Data:
MSB sba98765 LSB 4 3 2 1 0 - - v (ADC)
ADC Output Word; if v = 1, the data is invalid Offset Correction Byte
s6543210
sssss765
4 3 2 1 0 0 0 0 (Offset) Offset Byte shifted to align
with ADC data Gain Correction Word
sedcba98
7 6 5 4 3 2 1 0 (Gain)
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Compensation Steps: 1. Correct for Offset ADC MSB Offset MSB = #1 MSB #1 LSB 2. Take absolute value of the offset corrected ADC value if negative - the gain correction factor is computed assuming positive numbers, with sign restoration afterward. #2 MSB AGain MSB #2 LSB AGain LSB Also take absolute value of the gain correction word if negative. 3. Multiply by Gain Correction Word. If in DIFFERENTIAL mode, there are two gain correction values: one for positive ADC values, another for negative ADC values. Based on the sign of #2, use the appropriate Gain Correction Word. #2 MSB * AGain MSB = #3 #3 #3 #3 4. Round the result and discard the least significant two bytes (this is equivalent to dividing by 216). #3 0x00 = #4 MSB #4 LSB 5. Determine sign of the gain correction factor using the sign bits from step #2. If the offset corrected ADC value AND the gain correction word have the same sign, then the factor is positive and is left unchanged. If they have differing signs, then the factor is negative and should be multiplied by -1. #5 MSB #5 LSB 0x00 0x80 0x00 #3 #3 #3 AGain LSB #2 LSB Offset LSB ADC LSB
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6. Add the gain correction factor to the original offset corrected value. #5 MSB + #1 MSB = #6 MSB #6 LSB 7. Shift the result to the right, using the sign bit determined in step #1 above. This will allow for the detection of computational overflow. S-> Output Data The following is the output format of the corrected ADC value. MSB
svba9876
#5 LSB #1 LSB
#6 MSB
#6 LSB
LSB
543210--
The overflow bit in the corrected output indicates that the computed value was greater than the maximum logical value (+1023) or less than the minimum logical value (-1024). Unlike the hardware overflow bit, this is not a simple binary flag. For a normal sample (non-overflow), the sign and the overflow bit will match. If the sign bit and overflow bit do not match, a computational overflow has occurred.
Input Buffer Stage
Many applications require the measurement of an input voltage source with a high output impedance. This ADC provides a buffered input for such situations. The drawback of the buffered input is a limitation of the input range. When using unity gain buffered mode, the input signal must be prevented from coming too close to either VSS or VDD. See Table 138, Analog-to-Digital Converter Electrical Characteristics and Timing, on page 221 for details. This condition applies only to the input voltage level (with respect to ground) of each differential input signal. The actual differential input voltage magnitude may be less than 300 mV. The input range of the unbuffered ADC swings from VSS to VDD. Input signals smaller than 300 mV must use the unbuffered input mode. If these signals do not contain low output impedances, they might require off-chip buffering.
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Signals outside the allowable input range can be used without instability or device damage. Any ADC readings made outside the input range are subject to greater inaccuracy than specified.
Low-Power Operational Amplifier (LPO)
The LPO is a general-purpose operational amplifier. Each of the three ports of the amplifier is accessible from the package pins. The LPO contains only one pin configuration: ANA0 is the output/feedback node, ANA1 is the inverting input and ANA2 is the noninverting input. To use the LPO, it must be enabled in the Power Control Register 0 (PWRCTL0). The default state of the LPO is OFF. To use the LPO, the LPO bit must be cleared, turning it ON (Power Control Register 0 (PWRCTL0) on page 31). When making normal ADC measurements on ANA0 (measurements not involving the LPO output), the LPO bit must be OFF. Turning the LPO bit ON interferes with normal ADC measurements. Finally, this bit enables the amplifier even in STOP mode. If the amplifier is not required in STOP mode, disable it. Failing to perform this results in STOP mode currents greater than specified. As with other ADC measurements, any pins used for analog purposes must be configured as such in the GPIO registers (see Port A-D Alternate Function Sub-Registers on page 42). LPO output measurements are made on ANA0, as selected by the ANAIN[3:0] bits of ADC Control Register 0. It is also possible to make single-ended measurements on ANA1 and ANA2 while the amplifier is enabled, which is often useful for determining offset conditions. Differential measurements between ANA0 and ANA2 may be useful for noise cancellation purposes. If the LPO output is routed to the ADC, then the BUFFMODE[2:0] bits of ADC Control/Status Register 1 must also be configured for unity-gain buffered operation. Using the LPO in an unbuffered mode is not recommended. When either input is overdriven, the amplifier output saturates at the positive or negative supply voltage. No instability results.
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ADC Control Register Definitions
ADC Control Register 0
The ADC Control Register 0 (ADCCTL0) selects the analog input channel and initiates the analog-to-digital conversion. It also selects the voltage reference configuration.
Table 72. ADC Control Register 0 (ADCCTL0)
BITS FIELD RESET R/W ADDR
7 CEN 0 R/W
6 REFSELL 0 R/W
5 REFOUT 0 R/W
4 CONT 0 R/W F70H
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
ANAIN[3:0]
CEN--Conversion Enable 0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears this bit to 0 when a conversion is complete. 1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in progress, the conversion restarts. This bit remains 1 until the conversion is complete. REFSELL--Voltage Reference Level Select Low Bit; in conjunction with the High bit (REFSELH) in ADC Control/Status Register 1, this determines the level of the internal voltage reference; the following details the effects of {REFSELH, REFSELL}; note that this reference is independent of the Comparator reference 00= Internal Reference Disabled, reference comes from external pin 01= Internal Reference set to 1.0 V 10= Internal Reference set to 2.0 V (default) 11= Reserved REFOUT - Internal Reference Output Enable 0 = Reference buffer is disabled; Vref pin is available for GPIO or analog functions 1 = The internal ADC reference is buffered and driven out to the Vref pin Warning: When the ADC is used with an external reference ({REFSELH,REFSELL}=00), the REFOUT bit must be set to 0. CONT 0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock cycles (measurements of the internal temperature sensor take twice as long) 1 = Continuous conversion. ADC data updated every 256 system clock cycles after an initial 5129 clock conversion (measurements of the internal temperature sensor take twice as long)
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ANAIN[3:0]--Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8 Encore! XP(R) 4K Series. Refer to the chapter Pin Description on page 7 for information regarding the Port pins available with each package style. Do not enable unavailable analog inputs. Usage of these bits changes depending on the buffer mode selected in ADC Control/Status Register 1. For the reserved values, all input switches are disabled to avoid leakage or other undesirable operation. ADC samples taken with reserved bit settings are undefined. SINGLE-ENDED: 0000 = ANA0 (transimpedance amp output when enabled) 0001 = ANA1 (transimpedance amp inverting input) 0010 = ANA2 (transimpedance amp non-inverting input) 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Hold transimpedance input nodes (ANA1 and ANA2) to ground. 1101 = Reserved 1110 = Temperature Sensor. 1111 = Reserved. DIFFERENTIAL (non-inverting input and inverting input respectively): 0000 = ANA0 and ANA1 0001 = ANA2 and ANA3 0010 = ANA4 and ANA5 0011 = ANA1 and ANA0 0100 = ANA3 and ANA2 0101 = ANA5 and ANA4 0110 = ANA6 and ANA5 0111 = ANA0 and ANA2 1000 = ANA0 and ANA3 1001 = ANA0 and ANA4 1010 = ANA0 and ANA5 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Manual Offset Calibration Mode
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ADC Control/Status Register 1
The ADC Control/Status Register 1 (ADCCTL1) configures the input buffer stage, enables the threshold interrupts and contains the status of both threshold triggers. It is also used to select the voltage reference configuration.
Table 73. ADC Control/Status Register 1 (ADCCTL1)
BITS FIELD RESET R/W ADDR
7 1 R/W
6 0 R/W
5 ALMLST 0 R/W
4 ALMHEN 0 R/W F71H
3 ALMLEN 0 R/W
2 0 R/W
1 BUFMODE[2:0] 0 R/W
0 0 R/W
REFSELH ALMHST
REFSELH--Voltage Reference Level Select High Bit; in conjunction with the Low bit (REFSELL) in ADC Control Register 0, this determines the level of the internal voltage reference; the following details the effects of {REFSELH, REFSELL}; this reference is independent of the Comparator reference 00= Internal Reference Disabled, reference comes from external pin 01= Internal Reference set to 1.0 V 10= Internal Reference set to 2.0 V (default) 11= Reserved ALMHST--Alarm High Status; this bit can only be set by hardware and must be written with a 1 to clear 0= No alarm occurred. 1= A high threshold alarm occurred. ALMLST--Alarm Low Status; this bit can only be set by hardware and must be written with a 1 to clear 0= No alarm occurred. 1= A low threshold alarm occurred. ALMHEN--Alarm High Enable 0= Alarm interrupt for high threshold is disabled. The alarm status bit remains set when the alarm threshold is passed. 1= High threshold alarm interrupt is enabled. ALMLEN--Alarm Low Enable 0= Alarm interrupt for low threshold is disabled. The alarm status bit remains set when the alarm threshold is passed. 1= Low threshold alarm interrupt is enabled. BUFMODE[2:0] - Input Buffer Mode Select 000 = Single-ended, unbuffered input 001 = Single-ended, buffered input with unity gain
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010 = Reserved 011 = Reserved 100 = Differential, unbuffered input 101 = Differential, buffered input with unity gain 110 = Reserved 111 = Reserved
ADC Data High Byte Register
The ADC Data High Byte (ADCD_H) register contains the upper eight bits of the ADC output. The output is an 13-bit two's complement value. During a single-shot conversion, this value is invalid. Access to the ADC Data High Byte register is read-only. Reading the ADC Data High Byte register latches data in the ADC Low Bits register.
Table 74. ADC Data High Byte Register (ADCD_H)
BITS FIELD RESET R/W ADDR
7 X R
6 X R
5 X R
4 ADCDH X R F72H
3 X R
2 X R
1 X R
0 X R
ADCDH--ADC Data High Byte This byte contains the upper eight bits of the ADC output. These bits are not valid during a single-shot conversion. During a continuous conversion, the most recent conversion output is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Byte (ADCD_L) register contains the lower bits of the ADC output as well as an overflow status bit. The output is a 13-bit two's complement value. During a single-shot conversion, this value is invalid. Access to the ADC Data Low Byte register is read-only. Reading the ADC Data High Byte register latches data in the ADC Low Bits register.
Table 75. ADC Data Low Bits Register (ADCD_L)
BITS FIELD RESET R/W ADDR
7 X R
6 X R
5 ADCDL X R
4 X R F73H
3 X R
2 Reserved X R
1 X R
0 OVF X R
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ADCDL--ADC Data Low Bits These bits are the least significant five bits of the 13-bits of the ADC output. These bits are undefined after a Reset. Reserved--Must be undefined. OVF--Overflow Status 0= A hardware overflow did not occur in the ADC for the current sample. 1= A hardware overflow did occur in the ADC for the current sample, therefore the current sample is invalid.
ADC High Threshold Register
The ADC High Threshold (ADCTHH) register is used to set the trigger point above which an ADC sample causes a CPU interrupt.
Table 76. ADC High Threshold High Byte (ADCTHH)
BITS FIELD RESET R/W ADDR
7
6
5
4 ADCTHH FF
3
2
1
0
R/W
R/W
R/W
R/W F74H
R/W
R/W
R/W
R/W
ADCTHH--ADC High Threshold These bits are compared to the most significant 8 bits of the single-ended ADC value. If the ADC value exceeds this, an interrupt is asserted. The alarm function is not available in DIFFERENTIAL mode.
ADC Low Threshold Register
The ADC Low Threshold (ADCTLH) register is used to set the trigger point below which an ADC sample causes a CPU interrupt.
Table 77. ADC Low Threshold High Byte (ADCTLH)
BITS FIELD RESET R/W ADDR
7 0 R/W
6 0 R/W
5 0 R/W
4 ADCTLH 0 R/W F76H
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
ADCTLH--ADC Low Threshold These bits are compared to the most significant 8 bits of the single-ended ADC value. If
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the ADC value drops below this value an interrupt is asserted. The alarm function is not available in DIFFERENTIAL mode.
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Comparator
Overview
The Z8 Encore! XP(R) 4K Series devices feature a general purpose comparator that compares two analog input signals. These analog signals may be external stimulus from a pin (CINP and/or CINN) or internally generated signals. Both a programmable voltage reference and the temperature sensor output voltage are available internally. The output is available as an interrupt source or can be routed to an external pin.
CINP Pin Temperature Sensor INPSEL REFLVL INNSEL
To COUT Pin
+ To Interrupt Controller
Comparator Internal Reference CINN Pin
Figure 20.Comparator Block Diagram
Operation
When the positive comparator input exceeds the negative input by more than the specified hysteresis, the output is a logic HIGH. When the negative input exceeds the positive by more than the hysteresis, the output is a logic LOW. Otherwise, the comparator output retains its present value. Refer to Table 140, Comparator Electrical Characteristics, on page 223 for details.
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The comparator may be powered down to reduce supply current. See the Power Control Register 0 on page 30 for details. Caution: Because of the propagation delay of the comparator, it is not recommended to enable or reconfigure the comparator without first disabling interrupts and waiting for the comparator output to settle. Doing so can result in spurious interrupts. The following example shows how to safely enable the comparator:
di ld cmp0, r0 ; load some new configutation nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei
Comparator Control Register Definitions
Comparator Control Register
The Comparator Control Register (CMP0) configures the comparator inputs and sets the value of the internal voltage reference.
Table 78. Comparator Control Register (CMP0) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 1 R/W F90H 0 R/W 1 R/W 7 INPSEL 6 INNSEL 5 4 REFLVL 3 2 1 0
Reserved (20-/28-pin) REFLVL (8-pin) 0 R/W 0 R/W
INPSEL--Signal Select for Positive Input 0 = GPIO pin used as positive comparator input 1 = temperature sensor used as positive comparator input INNSEL--Signal Select for Negative Input 0 = internal reference disabled, GPIO pin used as negative comparator input 1 = internal reference enabled as negative comparator input REFLVL--Internal Reference Voltage Level (this reference is independent of the ADC voltage reference). Note that the 8-pin devices contain two additional LSBs for increased resolution. For 20-/28-pin devices:
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0000 = 0.0 V 0001 = 0.2 V 0010 = 0.4 V 0011 = 0.6 V 0100 = 0.8 V 0101 = 1.0 V (Default) 0110 = 1.2 V 0111 = 1.4 V 1000 = 1.6 V 1001 = 1.8 V 1010-1111 = Reserved For 8-pin devices: 000000 = 0.00V 000001 = 0.05V 000010 = 0.10V 000011 = 0.15V 000100 = 0.20V 000101 = 0.25V 000110 = 0.30V 000111 = 0.35V 001000 = 0.40V 001001 = 0.45V 001010 = 0.50V 001011 = 0.55V 001100 = 0.60V 001101 = 0.65V 001110 = 0.70V 001111 = 0.75V 010000 = 0.80V 010001 = 0.85V 010010 = 0.90V 010011 = 0.95V 010100 = 1.00V (Default) 010101 = 1.05V 010110 = 1.10V 010111 = 1.15V 011000 = 1.20V 011001 = 1.25V 011010 = 1.30V 011011 = 1.35V 011100 = 1.40V 011101 = 1.45V 011110 = 1.50V
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011111 = 1.55V 100000 = 1.60V 100001 = 1.65V 100010 = 1.70V 100011 = 1.75V 100100 = 1.80V
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Temperature Sensor
Overview
The on-chip Temperature Sensor allows the user the ability to measure temperature on the die with either the on-board ADC or on-board comparator. This block is factory calibrated for in-circuit software correction. Uncalibrated accuracy is significantly worse, therefore the temperature sensor is not recommended for uncalibrated use.
Temperature Sensor Operation
The on-chip temperature sensor is a PTAT (proportional to absolute temperature) topology. A pair of Flash option bytes contain the calibration data. The temperature sensor can be disabled by a bit in the Power Control Register 0 (page 30) to reduce power consumption. The temperature sensor can be directly read by the ADC to determine the absolute value of its output. The temperature sensor output is also available as an input to the comparator for threshold type measurement determination. The accuracy of the sensor when used with the comparator is substantially less than when measured by the ADC. If the temperature sensor is routed to the ADC, the ADC must be configured in unity-gain buffered mode (See Input Buffer Stage on page 122.) The value read back from the ADC is a signed number, although it is always positive. The sensor is factory-trimmed through the ADC using the external 2.0V reference. Unless the sensor is re-trimmed for use with a different reference, it is most accurate when used with the external 2.0V reference. Because this sensor is an on-chip sensor it is recommended that the user account for the difference between ambient and die temperature when inferring ambient temperature conditions. During normal operation, the die undergoes heating that will cause a mismatch between the ambient temperature and that measured by the sensor. For best results, the XP device should be placed into STOP mode for sufficient time such that the die and ambient temperatures converge (this time will be dependent on the thermal design of the system). The temperature sensor measurement should then be made immediately after recovery from STOP mode. The following equation defines the transfer function between the temperature sensor output voltage and the die temperature. This is needed for comparator threshold measurements. V = 0.01 * T + 0.65 (where T is the temperature in C; V is the sensor output in Volts)
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Assuming a compensated ADC measurement, the following equation defines the relationship between the ADC reading and the die temperature: T = (25/128)*(ADC - TSCAL) + 30 (where T is the temperature in C; ADC is the 10 bit compensated ADC value; and TSCAL is the temperature sensor calibration value) See Temperature Sensor Calibration Data on page 162 for the location of TSCAL.
Calibration
The temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30C. Accuracy decreases as measured temperatures move further from the calibration point.
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Flash Memory
Overview
The products in the Z8 Encore! XP(R) 4K Series features either 4KB (4096), 2KB (2048 bytes), or 1KB (1024) of non-volatile Flash memory with read/write/erase capability. The Flash Memory can be programmed and erased in-circuit by user code or through the OnChip Debugger. The Flash memory array is arranged in pages with 512 bytes per page. The 512-byte page is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64 bytes. For program/data protection, the Flash memory is also divided into sectors. In the Z8 Encore! XP(R) 4K Series, these sectors are 512 bytes in size; each sector maps to a page. Page and sector sizes are not equal for other members of the Z8 Encore!(R) family. The first 2 bytes of the Flash Program memory are used as Flash Option Bits. Refer to the chapter Flash Option Bits on page 148 for more information about their operation. Table 79 describes the Flash memory configuration for each device in the Z8 Encore! XP(R) 4K Series. Figure 21 illustrates the Flash memory arrangement.
Table 79. Z8 Encore! XP(R) 4K Series Flash Memory Configurations Flash Size KB (Bytes) 4 (4096) 2 (2048) 1 (1024) Flash Pages 8 4 2 Program Memory Addresses 0000H-0FFFH 0000H-07FFH 0000H-03FFH Flash Sector Size (bytes) 512 512 512
Part Number Z8F04xA Z8F02xA Z8F01xA
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4KB Flash Program Memory
Sector 7
Sector 6
Sector 5
2KB Flash Program Memory Addresses (hex) Addresses (hex) 07FF 0FFF Sector 3 0600 05FF 0E00 Sector 2 0DFF 0400 4 Pages/Sectors 03FF Sector 1 0C00 0200 0BFF 01FF Sector 0 0A00 0000 09FF
Sector 4 8 Pages/Sectors 512 Bytes each Sector 3 0600 Sector 2 05FF 0400 03FF Sector 1 0200 Sector 0 01FF 0000 0800 07FF 1KB Flash Program Memory Addresses (hex) 03FF Sector 1 0200 01FF 2 Pages/Sectors Sector 0 0000
Figure 21.Flash Memory Arrangement
Flash Information Area
The Flash information area is separate from program memory and is mapped to the address range FE00H to FFFFH. This area is readable but cannot be erased or overwritten. Factory trim values for the analog peripherals are stored here. Factory calibration data for the ADC is also stored here.
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Operation
The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental programming or erasure. These mechanism operate on the page, sector and full-memory levels. The Flow Chart in Figure 22 illustrates basic Flash Controller operation. The following subsections provide details about the various operations (Lock, Unlock, Byte Programming, Page Protect, Page Unprotect, Page Select, Page Erase, and Mass Erase) listed in Figure 22.
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Reset
Lock State 0
Write Page Select Register
Write FCTL
No
73H Yes Lock State 1 Writes to Page Select Register in Lock State 1 result in a return to Lock State 0
Write FCTL
No
8CH Yes Write Page Select Register
No
Page Select values match? Yes
Yes
Page in Protected Sector? Byte Program Write FCTL
No Page Unlocked Program/Erase Enabled
95H No
Yes
Page Erase
Figure 22.Flash Controller Operation Flow Chart
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Flash Operation Timing Using the Flash Frequency Registers
Before performing either a program or erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasing of the Flash with system clock frequencies ranging from 32 KHz (32768 Hz) through 20 MHz. The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash Frequency value must contain the system clock frequency (in KHz). This value is calculated using the following equation:
.
System Clock Frequency (Hz) FFREQ[15:0] = --------------------------------------------------------------------------1000
Caution: Flash programming and erasure are not supported for system clock frequencies below 32 KHz (32768 Hz) or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of the Z8 Encore! XP(R) 4K Series devices.
Flash Code Protection Against External Access
The user code contained within the Flash memory can be protected against external access by the on-chip debugger. Programming the FRP Flash Option Bit prevents reading of the user code with the On-Chip Debugger. Refer to the chapter Flash Option Bits on page 148 and the chapter On-Chip Debugger on page 167 for more information.
Flash Code Protection Against Accidental Program and Erasure
The Z8 Encore! XP(R) 4K Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by a combination of the Flash Option bits, the register locking mechanism, the page select redundancy and the sector level protection control of the Flash Controller. Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program Memory protection as listed in Table 80. Refer to the chapter Flash Option Bits on page 148 for more information.
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.
Table 80. Flash Code Protection Using the Flash Option Bits FWP 0 Flash Code Protection Description Programming and erasing disabled for all of Flash Program Memory. In user code programming, Page Erase, and Mass Erase are all disabled. Mass Erase is available through the On-Chip Debugger. Programming, Page Erase, and Mass Erase are enabled for all of Flash Program Memory.
1
Flash Code Protection Using the Flash Controller At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash memory. To program or erase the Flash memory, first write the Page Select Register with the target page. Unlock the Flash Controller by making two consecutive writes to the Flash Control register with the values 73H and 8CH, sequentially. The Page Select Register must be rewritten with the target page. If the two Page Select writes do not match, the controller reverts to a locked state. If the two writes match, the selected page becomes active. See Figure 22 for details. After unlocking a specific page, the user can enable either Page Program or Erase. Writing the value 95H causes a Page Erase only if the active page resides in a sector that is not protected. Any other value written to the Flash Control register locks the Flash Controller. Mass Erase is not allowed in the user code but only in through the Debug Port. After unlocking a specific page, the user can also write to any byte on that page. After a byte is written, the page remains unlocked, allowing for subsequent writes to other bytes on the same page. Further writes to the Flash Control Register cause the active page to revert to a locked state. Sector Based Flash Protection The final protection mechanism is implemented on a per-sector basis. The Flash memories of Z8 Encore!(R) devices are divided into at most 8 sectors. A sector is 1/8 of the total size of the Flash memory, unless this value is smaller than the page size, in which case the sector and page sizes are equal. On the Z8 Encore! XP(R) 4K Series devices, the sector size is 512 bytes, equal to the page size. The Sector Protect Register controls the protection state of each Flash sector. This register is shared with the Page Select Register. It is accessed by writing 73H followed by 5EH to the Flash controller. The next write to the Flash Control Register targets the Sector Protect Register. The Sector Protect Register is initialized to 0 on reset, putting each sector into an unprotected state. When a bit in the Sector Protect Register is written to 1, the corresponding
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sector can no longer be written or erased. After a bit of the Sector Protect Register has been set, it can not be cleared except by powering down the device.
Byte Programming
The Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is unlocked and Mass Erase is successfully completed, all Program Memory locations are available for byte programming. In contrast, when the Flash Controller is unlocked and Page Erase is successfully completed, only the locations of the selected page are available for byte programming. An erased Flash byte contains all 1's (FFH). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase commands. Byte Programming can be accomplished using the On-Chip Debugger's Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU User Manual (available for download at www.zilog.com)for a description of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To exit programming mode and lock the Flash, write any value to the Flash Control register, except the Mass Erase or Page Erase commands. Caution: The byte at each address of the Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted data at the target byte.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select register identifies the page to be erased. Only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95h to the Flash Control register initiates the Page Erase operation. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. If the Page Erase operation is performed using the On-Chip Debugger, poll the Flash Status register to determine when the Page Erase operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state.
Mass Erase
The Flash memory can also be Mass Erased using the Flash Controller, but only by using the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH. With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the
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value 63H to the Flash Control register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status register to determine when the Mass Erase operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Programming algorithms by controlling the Flash programming signals directly. Row programming is recommended for gang programming applications and large volume customers who do not require in-circuit initial programming of the Flash memory. Page Erase operations are also supported when the Flash Controller is bypassed. Please refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!(R) for more information about bypassing the Flash Controller. This document is available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger:
* * * * * * *
The Flash Write Protect option bit is ignored. The Flash Sector Protect register is ignored for programming and erase operations. Programming operations are not limited to the page selected in the Page Select register. Bits in the Flash Sector Protect register can be written to one or zero. The second write of the Page Select register to unlock the Flash Controller is not necessary. The Page Select register can be written when the Flash Controller is unlocked. The Mass Erase command is enabled through the Flash Control register.
Caution: For security reasons, the flash controller allows only a single page to be opened for write/erase. When writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page.
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Flash Control Register Definitions
Flash Control Register
The Flash Controller must be unlocked using the Flash Control (FCTL) register before programming or erasing the Flash memory. Writing the sequence 73H 8CH, sequentially, to the Flash Control register unlocks the Flash Controller. When the Flash Controller is unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the appropriate enable command to the FCTL. Page Erase applies only to the active page selected in Flash Page Select register. Mass Erase is enabled only through the On-Chip Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The Write-only Flash Control Register shares its Register File address with the read-only Flash Status Register
.
Table 81. Flash Control Register (FCTL) 7 0 W 6 0 W 5 0 W 4 FCMD 0 W FF8H 0 W 0 W 0 W 0 W 3 2 1 0
BITS FIELD RESET R/W ADDR
FCMD--Flash Command 73H = First unlock command. 8CH = Second unlock command. 95H = Page Erase command (must be third command in sequence to initiate Page Erase). 63H = Mass Erase command (must be third command in sequence to initiate Mass Erase). 5EH = Enable Flash Sector Protect Register Access
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Flash Status Register
The Flash Status (FSTAT) register indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its Register File address with the Write-only Flash Control Register.
Table 82. Flash Status Register (FSTAT) BITS FIELD RESET R/W ADDR 0 R 7 Reserved 0 R 0 R 0 R FF8H 0 R 6 5 4 3 FSTAT 0 R 0 R 0 R 2 1 0
Reserved--Must be 0. FSTAT--Flash Controller Status 000000 = Flash Controller locked. 000001 = First unlock command received (73H written). 000010 = Second unlock command received (8CH written). 000011 = Flash Controller unlocked. 000100 = Sector protect register selected. 001xxx = Program operation in progress. 010xxx = Page erase operation in progress. 100xxx = Mass erase operation in progress
Flash Page Select Register
The Flash Page Select (FPS) register shares address space with the Flash Sector Protect Register. Unless the Flash controller is unlocked and written with 5EH, writes to this address target the Flash Page Select Register. The register is used to select one of the 8 available Flash memory pages to be programmed or erased. Each Flash Page contains 512 bytes of Flash memory. During a Page Erase operation, all Flash memory having addresses with the most significant 7-bits given by FPS[6:0] are chosen for program/erase operation.
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Table 83. Flash Page Select Register (FPS) BITS FIELD RESET R/W ADDR 7 INFO_EN 0 R/W 0 R/W 0 R/W 0 R/W FF9H 6 5 4 3 PAGE 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
INFO_EN--Information Area Enable 0 = Information Area us not selected 1 = Information Area is selected. The Information Area is mapped into the Program Memory address space at addresses FE00H through FFFFH. PAGE--Page Select This 7-bit field identifies the Flash memory page for Page Erase and page unlocking. Program Memory Address[15:9] = PAGE[6:0]. For the Z8F04xx devices, the upper 4 bits must be zero. For Z8F02xx devices, the upper 5 bits must always be 0. For the Z8F01xx devices, the upper 6 bits must always be 0.
Flash Sector Protect Register
The Flash Sector Protect (FPROT) register is shared with the Flash Page Select Register. When the Flash Control Register is written with 73H followed by 5EH, the next write to this address targets the Flash Sector Protect Register. In all other cases, it targets the Flash Page Select Register. This register selects one of the 8 available Flash memory sectors to be protected. The reset state of each Sector Protect bit is an unprotected state. After a sector is protected by setting its corresponding register bit, it cannot be unprotected (the register bit cannot be cleared) without powering down the device.
Table 84. Flash Sector Protect Register (FPROT) BITS FIELD RESET R/W ADDR 7 SPROT7 0 R/W 6 SPROT6 0 R/W 5 SPROT5 0 R/W 4 SPROT4 0 R/W FF9H 3 SPROT3 0 R/W 2 SPROT2 0 R/W 1 SPROT1 0 R/W 0 SPROT0 0 R/W
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SPROT7-SPROT0--Sector Protection Each bit corresponds to a 512 byte Flash sector. For the Z8F04xx devices all bits are used. For the Z8F02xx devices, the upper 4 bits are unused. For the Z8F01xx devices, the upper 6 bits are unused.
Flash Frequency High and Low Byte Registers
The Flash Frequency High (FFREQH) and Low Byte (FFREQL) registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash Frequency value must contain the system clock frequency (in KHz) and is calculated using the following equation:.
System Clock Frequency FFREQ[15:0] = { FFREQH[7:0],FFREQL[7:0] } = -------------------------------------------------------------1000
Caution: The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device. Also, Flash programming and erasure is not supported for system clock frequencies below 20 KHz or above 20 MHz.
Table 85. Flash Frequency High Byte Register (FFREQH) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 0 R/W FFAH 7 6 5 4 FFREQH 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
FFREQH--Flash Frequency High Byte High byte of the 16-bit Flash Frequency value.
Table 86. Flash Frequency Low Byte Register (FFREQL) BITS FIELD RESET R/W ADDR 7 6 5 4 FFREQL 0 R/W FFBH 3 2 1 0
FFREQL--Flash Frequency Low Byte Low byte of the 16-bit Flash Frequency value.
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Flash Option Bits
Overview
Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! XP(R) 4K Series operation. The feature configuration data is stored in the Flash program memory and loaded into holding registers during Reset. The features available for control through the Flash Option Bits are:
* * * * * * * * * Operation
Watch-dog timer time-out response selection-interrupt or system reset Watch-dog timer Always on (enabled at Reset) The ability to prevent unwanted read access to user code in Program Memory The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory Voltage brown-out configuration-always enabled or disabled during STOP mode to reduce STOP mode power consumption Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator Factory trimming information for the internal precision oscillator and low voltage detection Factory calibration values for ADC, temperature sensor, and Watch-dog timer compensation Factory serialization and randomized lot identifier (optional)
Option Bit Configuration By Reset
Each time the Flash Option Bits are programmed or erased, the device must be Reset for the change to take effect. During any reset operation (System Reset, Power On Reset, or STOP Mode Recovery), the Flash Option Bits are automatically read from the Flash Program Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the Z8 Encore! XP(R) 4K Series. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access.
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Option Bit Types
User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits has been provided because these locations contain application-specific device configurations. The information contained here is lost when page 0 of the program memory is erased. Trim Option Bits The trim option bits are contained in the information page of the Flash memory. These bits are factory programmed values required to optimize the operation of onboard analog circuitry and cannot be permanently altered by the user. Program memory may be erased without endangering these values. It is possible to alter working values of these bits by accessing the Trim Bit Address and Data Registers, but these working values are lost after a power loss or any other reset event. There are 32 bytes of trim data. To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register. The next write to the Trim Bit Data register changes the working value of the target trim data byte. Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Register. The next read from the Trim Bit Data register returns the working value of the target trim data byte. Note: The trim address range is from information address 20-3F only. The remainder of the information page is not accessible through the trim bit address and data registers. Calibration Option Bits The calibration option bits are also contained in the information page. These bits are factory programmed values intended for use in software correcting the device's analog performance. To read these values, the user code must employ the LDC instruction to access the information area of the address space as defined in See Flash Information Area on page 15. Serialization Bits As an optional feature, ZiLOG is able to provide factory-programmed serialization. For serialized products, the individual devices will be programmed with unique serial numbers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist. These serial numbers are stored in the flash information page (see Reading the Flash Information Page on page 150 and Serialization Data on page 159 for more details) and are unaffected by mass erasure of the device's flash memory.
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Randomized Lot Identification Bits As an optional feature, ZiLOG is able to provide a factory-programmed random lot identifier. With this feature, all devices in a given production lot will be programmed with the same random number. This random number is uniquely regenerated for each successive production lot and is not likely to be repeated. The randomized lot identifier is a 32 byte binary value, stored in the flash information page (see Reading the Flash Information Page on page 150 and Randomized Lot Identifier on page 159 for more details) and is unaffected by mass erasure of the device's flash memory.
Reading the Flash Information Page
The following code example shows how to read data from the flash information area.
; get value at info address 60 (FE60h) ldx FPS, #%80 ; enable access to flash info page ld R0, #%FE ld R1, #%60 ldc R2, @RR0 ; R2 now contains the calibration value
Flash Option Bit Control Register Definitions
Trim Bit Address Register
The Trim Bit Address (TRMADR) register contains the target address for an access to the trim option bits.
Table 87. Trim Bit Address Register (TRMADR) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 7 6 5 0 R/W 4 0 R/W FF6H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
TRMADR - Trim Bit Address (00H to 1FH)
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Trim Bit Data Register
The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim option bits.
Table 88. Trim Bit Data Register (TRMDR) BITS FIELD RESET R/W ADDR 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W FF7H 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
TRMDR - Trim Bit Data
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved for the user-programmable Flash option bits.
Flash Program Memory Address 0000H
Table 89. Flash Option Bits at Program Memory Address 0000H BITS FIELD RESET R/W ADDR 7 U R/W 6 U R/W 5 U R/W 4 U R/W 3 VBO_AO U R/W 2 FRP U R/W 1 Reserved U R/W 0 FWP U R/W
WDT_RES WDT_AO
OSC_SEL[1:0]
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES--Watch-Dog Timer Reset 0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request. 1 = Watch-Dog Timer time-out causes a system reset. This setting is the default for unprogrammed (erased) Flash. WDT_AO--Watch-Dog Timer Always On 0 = Watch-Dog Timer is automatically enabled upon application of system power. WatchDog Timer can not be disabled. 1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled, the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This setting is the default for unprogrammed (erased) Flash.
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OSC_SEL[1:0]--Oscillator Mode Selection 00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). 10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 5.0MHz). 11 = Maximum power for use with high frequency crystals (5.0MHz to 20.0MHz). This setting is the default for unprogrammed (erased) Flash. VBO_AO--Voltage Brown-Out Protection Always On 0 = Voltage Brown-Out Protection is disabled in STOP mode to reduce total power consumption. 1 = Voltage Brown-Out Protection is always enabled including during STOP mode. This setting is the default for unprogrammed (erased) Flash. FRP--Flash Read Protect 0 = User program code is inaccessible. Limited control features are available through the On-Chip Debugger. 1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash. Reserved--Must be 1. FWP--Flash Write Protect This Option Bit provides Flash Program Memory protection: 0 = Programming and erasure disabled for all of Flash Program Memory. Programming, Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available using the On-Chip Debugger. 1 = Programming, Page Erase, and Mass Erase are enabled for all of Flash program memory.
Flash Program Memory Address 0001H
Table 90. Flash Options Bits at Program Memory Address 0001H BITS FIELD RESET R/W ADDR U R/W 7 6 Reserved U R/W U R/W 5 4 XTLDIS U R/W U R/W U R/W 3 2 Reserved U R/W U R/W 1 0
Program Memory 0001H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved--Must be 1. XTLDIS--State of Crystal Oscillator at Reset:
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Note:
This bit only enables the crystal oscillator. Its selection as system clock must be done manually. 0 = Crystal oscillator is enabled during reset, resulting in longer reset timing 1 = Crystal oscillator is disabled during reset, resulting in shorter reset timing
Trim Bit Address Space
Trim Bit Address 0000H
Table 91. Trim Options Bits at Address 0000H BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 Reserved U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 0020H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved-- Altering this register may result in incorrect device operation.
Trim Bit Address 0001H
Table 92. Trim Option Bits at 0001H BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 Reserved U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 0021H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved-- Altering this register may result in incorrect device operation.
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Trim Bit Address 0002H
Table 93. Trim Option Bits at 0002H (TIPO) BITS FIELD RESET R/W ADDR Note: U = Unchanged by Reset. R/W = Read/Write. 7 6 5 4 IPO_TRIM U R/W Information Page Memory 0022H 3 2 1 0
IPO_TRIM--Internal Precision Oscillator Trim Byte Contains trimming bits for Internal Precision Oscillator.
Trim Bit Address 0003H
Note: The LVD is available on 8-pin devices only.
Table 94. Trim Option Bits at Address 0003H (TLVD) BITS FIELD RESET R/W ADDR U R/W 7 6 Reserved U R/W U R/W U R/W U R/W 5 4 3 2 LVD_TRIM U R/W U R/W U R/W 1 0
Information Page Memory 0023H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved--Must be 1. LVD_TRIM--Low Voltage Detect Trim
This trimming affects the low voltage detection threshold. Each LSB represents a 50mV change in the threshold level. Alternatively, the low voltage threshold may be computed from the options bit value by the following equation:
LVD_LVL = 3.2V - LVD_TRIM * 0.05V
LVD Threshold (V) LVD_TRIM 00000 00001 Minimum TBD TBD Typical 3.20 3.15 Maximum Description TBD TBD Maximum LVD threshold
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LVD Threshold (V) LVD_TRIM 00010 00011 00100 to 01010 01010 to 11111 Minimum TBD TBD TBD Typical 3.10 3.05 3.00 to 2.79 2.70 to 1.65 Maximum Description TBD TBD TBD Default on Reset and to be programmed into Flash before customer delivery to ensure 2.7V operation. TBD Minimum LVD threshold
TBD
Trim Bit Address 0004H
Table 95. Trim Option Bits at 0004H BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 Reserved U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 0024H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved-- Altering this register may result in incorrect device operation.
ZiLOG Calibration Data
ADC Calibration Data
Table 96. ADC Calibration Bits BITS FIELD RESET R/W ADDR U R/W U R/W U R/W 7 6 5 4 ADC_CAL U R/W U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 0060H-007DH
Note: U = Unchanged by Reset. R/W = Read/Write.
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ADC_CAL--Analog to Digital Converter Calibration Values Contains factory calibrated values for ADC gain and offset compensation. Each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. These values are read by user software to compensate ADC measurements as detailed in Software Compensation Procedure Using Factory Calibration Data on page 119. The location of each calibration byte is provided in Table 97.
Table 97. ADC Calibration Data Location Info Page Address 60 08 09 63 0A 0B 66 0C 0D 69 0E 0F 6C 10 11 6F 12 13 30 31 72 Memory Address FE60 FE08 FE09 FE63 FE0A FE0B FE66 FE0C FE0D FE69 FE0E FE0F FE6C FE10 FE11 FE6F FE12 FE13 FE30 FE31 FE72 Compensation Usage Offset Gain High Byte Gain Low Byte Offset Gain High Byte Gain Low Byte Offset Gain High Byte Gain Low Byte Offset Gain High Byte Gain Low Byte Offset Gain High Byte Gain Low Byte Offset Positive Gain High Byte Positive Gain Low Byte Negative Gain High Byte Negative Gain Low Byte Offset ADC Mode Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single-Ended Unbuffered Single Ended 1x Buffered Single Ended 1x Buffered Single Ended 1x Buffered Single Ended 1x Buffered Single Ended 1x Buffered Single Ended 1x Buffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Reference Type Internal 2.0V Internal 2.0V Internal 2.0V Internal 1.0V Internal 1.0V Internal 1.0V External 2.0V External 2.0V External 2.0V Internal 2.0V Internal 2.0V Internal 2.0V External 2.0V External 2.0V External 2.0V Internal 2.0V Internal 2.0V Internal 2.0V Internal 2.0V Internal 2.0V Internal 1.0V
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Table 97. ADC Calibration Data Location (Continued) Info Page Address 14 15 32 33 75 16 17 34 35 78 18 19 36 37 7B 1A 1B Memory Address FE14 FE15 FE32 FE33 FE75 FE16 FE17 FE34 FE35 FE78 FE18 FE19 FE36 FE37 FE7B FE1A FE1B Compensation Usage Positive Gain High Byte Positive Gain Low Byte Negative Gain High Byte Negative Gain Low Byte Offset Positive Gain High Byte Positive Gain Low Byte Negative Gain High Byte Negative Gain Low Byte Offset Positive Gain High Byte Positive Gain Low Byte Negative Gain High Byte Negative Gain Low Byte Offset Positive Gain High Byte Positive Gain Low Byte ADC Mode Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential Unbuffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Differential 1x Buffered Reference Type Internal 1.0V Internal 1.0V Internal 1.0V Internal 1.0V External 2.0V External 2.0V External 2.0V External 2.0V External 2.0V Internal 2.0V Internal 2.0V Internal 2.0V Internal 2.0V Internal 2.0V External 2.0V External 2.0V External 2.0V
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Table 97. ADC Calibration Data Location (Continued) Info Page Address 38 39 Memory Address FE38 FE39 Compensation Usage Negative Gain High Byte Negative Gain Low Byte ADC Mode Differential 1x Buffered Differential 1x Buffered Reference Type External 2.0V External 2.0V
Watchdog Timer Calibration Data
Table 98. Watchdog Calibration High Byte at 007EH (WDTCALH) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W 7 6 5 4 U R/W 3 U R/W 2 U R/W 1 U R/W 0 U R/W
WDTCALH
Information Page Memory 007EH
Note: U = Unchanged by Reset. R/W = Read/Write.
WDTCALH--Watchdog Timer Calibration High Byte The WDTCALH and WDTCALL bytes, when loaded into the watchdog timer reload registers result in a one second timeout at room temperature and 3.3V supply voltage. To use the Watch-Dog Timer calibration, user code must load WDTU with 0x00, WDTH with WDTCALH and WDTL with WDTCALL.
Table 99. Watchdog Calibration Low Byte at 007FH (WDTCALL) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W 7 6 5 4 WDTCALL U R/W U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 007FH
Note: U = Unchanged by Reset. R/W = Read/Write.
WDTCALL--Watchdog Timer Calibration Low Byte The WDTCALH and WDTCALL bytes, when loaded into the watchdog timer reload registers result in a one second timeout at room temperature and 3.3V supply voltage. To use the watchdog timer calibration, user code must load WDTU with 0x00, WDTH with WDTCALH and WDTL with WDTCALL.
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Serialization Data
Table 100. Serial Number at 001C - 001F (S_NUM) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 S_NUM U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 001C-001F
Note: U = Unchanged by Reset. R/W = Read/Write.
S_NUM-- Serial Number Byte The serial number is a unique four-byte binary value.
Table 101. Serialization Data Locations Info Page Address 1C 1D 1E 1F Memory Address FE1C FE1D FE1E FE1F Usage Serial Number Byte 3 (most significant) Serial Number Byte 2 Serial Number Byte 1 Serial Number Byte 0 (least significant)
Randomized Lot Identifier
Table 102. Lot Identification Number (RAND_LOT) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W 7 6 5 4 U R/W 3 U R/W 2 U R/W 1 U R/W 0 U R/W
RAND_LOT
Interspersed throughout Information Page Memory
Note: U = Unchanged by Reset. R/W = Read/Write.
RAND_LOT-- Randomized Lot ID The randomized lot ID is a 32-byte binary value that changes for each production lot.
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Table 103. Randomized Lot ID Locations Info Page Address 3C 3D 3E 3F 58 59 5A 5B 5C 5D 5E 5F 61 62 64 65 67 68 6A 6B 6D 6E 70 71 73 74 76 77 Memory Address FE3C FE3D FE3E FE3F FE58 FE59 FE5A FE5B FE5C FE5D FE5E FE5F FE61 FE62 FE64 FE65 FE67 FE68 FE6A FE6B FE6D FE6E FE70 FE71 FE73 FE74 FE76 FE77 Usage Randomized Lot ID Byte 31 (most significant) Randomized Lot ID Byte 30 Randomized Lot ID Byte 29 Randomized Lot ID Byte 28 Randomized Lot ID Byte 27 Randomized Lot ID Byte 26 Randomized Lot ID Byte 25 Randomized Lot ID Byte 24 Randomized Lot ID Byte 23 Randomized Lot ID Byte 22 Randomized Lot ID Byte 21 Randomized Lot ID Byte 20 Randomized Lot ID Byte 19 Randomized Lot ID Byte 18 Randomized Lot ID Byte 17 Randomized Lot ID Byte 16 Randomized Lot ID Byte 15 Randomized Lot ID Byte 14 Randomized Lot ID Byte 13 Randomized Lot ID Byte 12 Randomized Lot ID Byte 11 Randomized Lot ID Byte 10 Randomized Lot ID Byte 9 Randomized Lot ID Byte 8 Randomized Lot ID Byte 7 Randomized Lot ID Byte 6 Randomized Lot ID Byte 5 Randomized Lot ID Byte 4
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Table 103. Randomized Lot ID Locations (Continued) Info Page Address 79 7A 7C 7D Memory Address FE79 FE7A FE7C FE7D Usage Randomized Lot ID Byte 3 Randomized Lot ID Byte 2 Randomized Lot ID Byte 1 Randomized Lot ID Byte 0 (least significant)
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Temperature Sensor Calibration Data
Table 104. Temperature Sensor Calibration High Byte at 003A (TSCALH) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 TSCALH U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 003A
Note: U = Unchanged by Reset. R/W = Read/Write.
TSCALH - Temperature Sensor Calibration High Byte The TSCALH and TSCALL bytes combine to form the temperature sensor offset calibration value. For usage details, see Temperature Sensor Operation on page 134.
Table 105. Temperature Sensor Calibration Low Byte at 003B (TSCALL) BITS FIELD RESET R/W ADDR U R/W U R/W U R/W U R/W 7 6 5 4 TSCALL U R/W U R/W U R/W U R/W 3 2 1 0
Information Page Memory 003B
Note: U = Unchanged by Reset. R/W = Read/Write.
TSCALL - Temperature Sensor Calibration Low Byte The TSCALH and TSCALL bytes combine to form the temperature sensor offset calibration value. For usage details, see Temperature Sensor Operation on page 134.
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Non-Volatile Data Storage
Overview
The Z8 Encore! XP(R) 4K Series devices contain a non-volatile data storage (NVDS) element of up to 128 bytes. This memory can perform over 100,000 write cycles.
Operation
The NVDS is implemented by special purpose ZiLOG software stored in areas of program memory not accessible to the user. These special-purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the Flash. Note: Different members of the Z8 Encore! XP(R) 4K Series feature multiple NVDS array sizes. See Z8 Encore! XP(R) 4K Series Family Part Selection Guide on page 2 for details.
NVDS Code Interface
Two routines are required to access the NVDS: a write routine and a read routine. Both of these routines are accessed with a CALL instruction to a pre-defined address outside of the user-accessible program memory. Both the NVDS address and data are single-byte values. Because these routines disturb the working register set, user code must ensure that any required working register values are preserved by pushing them onto the stack or by changing the working register pointer just prior to NVDS execution. During both read and write accesses to the NVDS, interrupt service is NOT disabled. Any interrupts that occur during the NVDS execution must take care not to disturb the working register and existing stack contents or else the array may become corrupted. Disabling interrupts before executing NVDS operations is recommended. Use of the NVDS requires 15 bytes of available stack space. Also, the contents of the working register set are overwritten. For correct NVDS operation, the Flash Frequency Registers must be programmed based on the system clock frequency (See Flash Operation Timing Using the Flash Frequency Registers on page 140).
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Byte Write
To write a byte to the NVDS array, the user code must first push the address, then the data byte onto the stack. The user code issues a CALL instruction to the address of the bytewrite routine (0x10B3). At the return from the sub-routine, the write status byte resides in working register R0. The bit fields of this status byte are defined in Table 106. The contents of the status byte are undefined for write operations to illegal addresses. Also, user code should pop the address and data bytes off the stack. The write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user. Sufficient memory must be available for this stack usage. Because of the flash memory architecture, NVDS writes exhibit a non-uniform execution time. In general, a write takes 251s (assuming a 20MHz system clock). Every 400 to 500 writes, however, a maintenance operation is necessary. In this rare occurrence, the write takes up to 61ms to complete. Slower system clock speeds result in proportionally higher execution times. NVDS byte writes to invalid addresses (those exceeding the NVDS array size) have no effect. Illegal write operations have a 2s execution time.
Table 106. Write Status Byte BITS FIELD DEFAULT VALUE 0 0 7 6 Reserved 0 0 5 4 3 RCPY 0 2 PF 0 1 AWE 0 0 DWE 0
Reserved--Must be 0. RCPY--Recopy Subroutine Executed A recopy subroutine was executed. These operations take significantly longer than a normal write operation. PF--Power Failure Indicator A power failure or system reset occurred during the most recent attempted write to the NVDS array. AW--Address Write Error An address byte failure occurred during the most recent attempted write to the NVDS array. DWE--Data Write Error A data byte failure occurred during the most recent attempted write to the NVDS array.
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Byte Read
To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a CALL instruction to the address of the byte-read routine (0x1000). At the return from the sub-routine, the read byte resides in working register R0, and the read status byte resides in working register R1. The contents of the status byte are undefined for read operations to illegal addresses. Also, the user code should pop the address byte off the stack. The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. Sufficient memory must be available for this stack usage. Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution time. A read operation takes between 44 s and 489 s (assuming a 20 MHz system clock). Slower system clock speeds result in proportionally higher execution times. NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return 0xff. Illegal read operations have a 2 s execution time. The status byte returned by the NVDS read routine is zero for successful read, as determined by a CRC check. If the status byte is non-zero, there was a corrupted value in the NVDS array at the location being read. In this case, the value returned in R0 is the byte most recently written to the array that does not have a CRC error.
Power Failure Protection
The NVDS routines employ error checking mechanisms to ensure a power failure endangers only the most recently written byte. Bytes previously written to the array are not perturbed. A system reset (such as a pin reset or watchdog timer reset) that occurs during a write operation also perturbs the byte currently being written. All other bytes in the array are unperturbed.
Optimizing NVDS Memory Usage for Execution Speed
As Table 107 shows, the NVDS read time varies drastically, this discrepancy being a trade-off for minimizing the frequency of writes that require post-write page erases. The NVDS read time of address N is a function of the number of writes to addresses other than N since the most recent write to address N, as well as the number of writes since the most recent page erase. Neglecting effects caused by page erases and results caused by the initial condition in which the NVDS is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 s, up to a maximum of (511-NVDS_SIZE) s.
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Table 107. NVDS Read Time Minimum Latency 875 876 883 4973 4971 4984 43 31 Maximum Latency 9961 8952 7609 5009 5013 5023 43 31
Operation Read (16 byte array) Read (64 byte array) Read (128 byte array) Write (16 byte array) Write (64 byte array) Write (128 byte array) Illegal Read Illegal Write
If NVDS read performance is critical to your software architecture, there are some things you can do to optimize your code for speed, listed in order from most helpful to least helpful:
*
Periodically refresh all addresses that are used. The optimal use of NVDS in terms of speed is to rotate the writes evenly among all addresses planned to use, bringing all reads closer to the minimum read time. Because the minimum read time is much less than the write time, however, actual speed benefits are not always realized. Use as few unique addresses as possible: this helps to optimize the impact of refreshing as well as minimize the requirement for it.
*
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On-Chip Debugger
Overview
The Z8 Encore! XP(R) devices contain an integrated On-Chip Debugger (OCD) that provides advanced debugging features including:
* * * * * Architecture
Reading and writing of the register file Reading and writing of program and data memory Setting of breakpoints and watchpoints Executing eZ8 CPU instructions Debug pin sharing with general-purpose input-output function to maximize pins available to the user (8-pin product only)
The on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud detector/generator, and debug controller. Figure 23 illustrates the architecture of the on-chip debugger
System Clock
Auto-Baud Detector/Generator eZ8 CPU Control Transmitter Debug Controller
DBG Pin
Receiver
Figure 23.On-Chip Debugger Block Diagram
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Operation
OCD Interface
The on-chip debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional, open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS-232. This pin creates an interface from the Z8 Encore! XP(R) 4K Series products to the serial port of a host PC using minimal external hardware.Two different methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 24 and 25 . The recommended method is the buffered implementation depicted in Figure 25. The DBG pin must always be connected to VDD through an external pull-up resistor. Caution: For operation of the on-chip debugger, all power pins (VDD and AVDD) must be supplied with power, and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must always be connected to VDD through an external pull-up resistor to insure proper operation.
VDD RS-232 Transceiver RS-232 TX
Schottky Diode
10KOhm DBG Pin
RS-232 RX
Figure 24.Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1)
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VDD RS-232 Transceiver RS-232 TX
Open-Drain Buffer
10KOhm DBG Pin
RS-232 RX
Figure 25.Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
* * * * * * * *
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions The system clock operates unless in STOP mode All enabled on-chip peripherals operate unless in STOP mode Automatically exits HALT mode Constantly refreshes the Watch-Dog Timer, if enabled
Entering DEBUG Mode The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruction. If the DBG pin is held Low during the most recent clock cycle of system reset, the part enters DEBUG mode upon exiting system reset. (20-/28-pin products only.) If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it will be pulled high. At this point, the PA0/DBG pin may be used to autobaud and cause the device to enter DEBUG mude. See OCD Unlock Sequence (8-Pin Devices Only) on page 171.
Exiting DEBUG Mode The device exits DEBUG mode following any of these operations:
*
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Clearing the DBGMODE bit in the OCD Control Register to 0.
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* * * * *
Power-on reset Voltage Brown-Out reset Watch-Dog Timer reset Asserting the RESET pin Low to initiate a Reset. Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1.5 Stop bits as shown in Figure 26.
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
Figure 26.OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock frequencies, the On-Chip Debugger contains an Auto-Baud Detector/Generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the host is the character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7 data bits), framed between High bits. The Auto-Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly. The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud rate is the system clock frequency divided by 512. For optimal operation with asynchronous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. The maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by 4, but this theoretical maximum is possible only for low noise designs with clean signals. Table 108 lists minimum and recommended maximum baud rates for sample crystal frequencies.
Table 108. OCD Baud-Rate Limits System Clock Frequency (MHz) 20.0 Recommended Maximum Baud Rate (Kbps) 2500.0 Recommended Standard PC Baud Rate (bps) 1,843,200 Minimum Baud Rate (Kbps) 39
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Table 108. OCD Baud-Rate Limits System Clock Frequency (MHz) 1.0 0.032768 (32KHz) Recommended Maximum Baud Rate (Kbps) 125.0 4.096 Recommended Standard PC Baud Rate (bps) 115,200 2400 Minimum Baud Rate (Kbps) 1.95 0.064
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud Detector/Generator resets. Reconfigure the Auto-Baud Detector/Generator by sending
80H.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
* * *
Serial Break (a minimum of nine continuous bits Low) Framing Error (received Stop bit is Low) Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress, transmits a four character long Serial Break back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore! XP(R) 4K Series devices or when recovering from an error. A Serial Break from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Control register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character.
OCD Unlock Sequence (8-Pin Devices Only)
Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the DBG pin. If this squence is not completed during a system reset, then the PA0/ DBG pin functions only as a GPIO pin. The following sequence unlocks the DBG pin: 1. Hold PA2/RESET Low.
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2. Wait 5ms for the internal reset sequence to complete. 3. Send the following bytes serially to the debug pin:
DBG 80H (autobaud) DBG EBH DBG 5AH DBG 70H DBG CDH (32-bit unlock key)
4. Release PA2/RESET. The PA0/DBG pin is now identical in function to that of the DBG pin on the 20-/28-pin device. To enter DEBUG mode, re-autobaud and write 80H to the OCD control register. (See On-Chip Debugger Commands on page 172.)
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD enters DEBUG mode and idles the eZ8 CPU. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction. Breakpoints in Flash Memory The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a byte in Flash memory. To implement a Breakpoint, write 00H to the required break address, overwriting the current instruction. To remove a Breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the original data.
Runtime Counter
The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles between Breakpoints. The counter starts counting when the On-Chip Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches the maximum count of FFFFH.
On-Chip Debugger Commands
The host communicates to the on-chip debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the user code and control registers are protected by programming the Flash Read Protect Option bit (FRP). The Flash Read Protect Option bit prevents the code in memory from being read out of the Z8 Encore! XP(R) 4K Series products. When this option is enabled, several of the OCD
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commands are disabled. Table 109 on page 177 is a summary of the On-chip debugger commands. Each OCD command is described in further detail in the bulleted list following this table. Table 109 also indicates those commands that operate when the device is not in DEBUG mode (normal operation) and those commands that are disabled by programming the Flash Read Protect Option bit.
Command Byte 00H 01H 02H 03H 04H 05H 06H 07H 08H Enabled when NOT in DEBUG mode? Yes - Yes - Yes Yes - - - Disabled by Flash Read Protect Option Bit - - - - Cannot clear DBGMODE bit - Disabled Disabled Only writes of the Flash Memory Control registers are allowed. Additionally, only the Mass Erase command is allowed to be written to the Flash Control register. Disabled Disabled Disabled Yes - - - Disabled Disabled Disabled -
Debug Command Read OCD Revision Reserved Read OCD Status Register Read Runtime Counter Write OCD Control Register Read OCD Control Register Write Program Counter Read Program Counter Write Register
Read Register Write Program Memory Read Program Memory Write Data Memory Read Data Memory Read Program Memory CRC Reserved Step Instruction Stuff Instruction Execute Instruction Reserved
09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H-FFH
- - - - - - - - - - -
In the following bulleted list of OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by 'DBG Command/Data'. Data sent from the On-Chip Debugger back to the host is identified by 'DBG Data'
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*
Read OCD Revision (00H)--The Read OCD Revision command determines the version of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes.
DBG 00H DBG OCDRev[15:8] (Major revision number) DBG OCDRev[7:0] (Minor revision number)
*
Read OCD Status Register (02H)--The Read OCD Status Register command reads the OCDSTAT register.
DBG 02H DBG OCDSTAT[7:0]
*
Read Runtime Counter (03H)--The Runtime Counter counts system clock cycles in between Breakpoints. The 16-bit Runtime Counter counts up from 0000H and stops at the maximum count of FFFFH. The Runtime Counter is overwritten during the Write Memory, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff Instruction, and Execute Instruction commands.
DBG 03H DBG RuntimeCounter[15:8] DBG RuntimeCounter[7:0]
*
Write OCD Control Register (04H)--The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Flash Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device.
DBG 04H DBG OCDCTL[7:0]
*
Read OCD Control Register (05H)--The Read OCD Control Register command reads the value of the OCDCTL register.
DBG 05H DBG OCDCTL[7:0]
*
Write Program Counter (06H)--The Write Program Counter command writes the data that follows to the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are discarded.
DBG 06H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
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*
Read Program Counter (07H)--The Read Program Counter command reads the value in the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this command returns FFFFH.
DBG 07H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
*
Write Register (08H)--The Write Register command writes data to the Register File. Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to 0). If the device is not in DEBUG mode, the address and data values are discarded. If the Flash Read Protect Option bit is enabled, only writes to the Flash Control Registers are allowed and all other register write data values are discarded.
DBG DBG DBG DBG DBG

08H {4'h0,Register Address[11:8]} Register Address[7:0] Size[7:0] 1-256 data bytes
*
Read Register (09H)--The Read Register command reads data from the Register File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this command returns FFH for all the data values.
DBG DBG DBG DBG DBG

09H {4'h0,Register Address[11:8] Register Address[7:0] Size[7:0] 1-256 data bytes
*
Write Program Memory (0AH)--The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG

0AH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Program Memory (0BH)--The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions.
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Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this command returns FFH for the data.
DBG DBG DBG DBG DBG DBG

0BH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Write Data Memory (0CH)--The Write Data Memory command writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG

0CH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Data Memory (0DH)--The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG mode, this command returns FFH for the data.
DBG DBG DBG DBG DBG DBG

0DH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Program Memory CRC (0EH)--The Read Program Memory CRC command computes and returns the Cyclic Redundancy Check (CRC) of Program Memory using the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory.
DBG 0EH DBG CRC[15:8] DBG CRC[7:0]
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*
Step Instruction (10H)--The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command.
DBG 10H
*
Stuff Instruction (11H)--The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command.
DBG 11H DBG opcode[7:0]
*
Execute Instruction (12H)--The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, this command reads and discards one byte.
DBG 12H DBG 1-5 byte opcode
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register controls the state of the On-Chip Debugger. This register is used to enter or exit DEBUG mode and to enable the BRK instruction. It can also reset the Z8 Encore! XP(R) 4K Series device. A reset and stop function can be achieved by writing 81H to this register. A reset and go function can be achieved by writing 41H to this register. If the device is in DEBUG mode, a run function can be implemented by writing 40H to this register.
.
Table 109. OCD Control Register (OCDCTL) 7 DBGMODE 0 R/W 6 BRKEN 0 R/W 5 DBGACK 0 R/W 0 R 0 R 4 3 Reserved 0 R 0 R 2 1 0 RST 0 R/W
BITS FIELD RESET R/W
DBGMODE--Debug Mode The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
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stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the device. It cannot be written to 0. 0 = The Z8 Encore! XP(R) 4K Series device is operating in NORMAL mode. 1 = The Z8 Encore! XP(R) 4K Series device is in DEBUG mode. BRKEN--Breakpoint Enable This bit controls the behavior of the BRK instruction (opcode 00H). By default, Breakpoints are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1, when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automatically set to 1. 0 = Breakpoints are disabled. 1 = Breakpoints are enabled. DBGACK--Debug Acknowledge This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. Reserved--Must be 0. RST--Reset Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared to 0 at the end of reset. 0 = No effect. 1 = Reset the Flash Read Protect Option Bit device.
OCD Status Register
The OCD Status register reports status information about the current state of the debugger and the system.
Table 110. OCD Status Register (OCDSTAT) BITS FIELD RESET R/W 7 DBG 0 R 6 HALT 0 R 5 FRPENB 0 R 0 R 0 R 4 3 2 Reserved 0 R 0 R 0 R 1 0
DBG--Debug Status 0 = NORMAL mode 1 = DEBUG mode
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HALT--HALT Mode 0 = Not in HALT mode 1 = In HALT mode FRPENB--Flash Read Protect Option Bit Enable 0 = FRP bit enabled, that allows disabling of many OCD commands 1 = FRP bit has no effect Reserved--Must be 0.
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Oscillator Control
Overview
The Z8 Encore! XP(R) 4K Series devices uses five possible clocking schemes, each userselectable:
* * * * *
Internal precision trimmed RC oscillator (IPO) On-chip oscillator using off-chip crystal or resonator On-chip oscillator using external RC network External clock drive On-chip low precision Watch-Dog Timer oscillator
In addition, Z8 Encore! XP(R) 4K Series devices contain clock failure detection and recovery circuitry, allowing continued operation despite a failure of the system clock oscillator.
Operation
This chapter discusses the logic used to select the system clock and handle primary oscillator failures. A description of the specific operation of each oscillator is outlined elsewhere in this document. The detailed description of the Watch-Dog Timer Oscillator starts on page 83, the Internal Precision Oscillator description begins on page 190, and the chapter outlining the Crystal Oscillator begins on page 185 of this document.
System Clock Selection
The oscillator control block selects from the available clocks. Table 111 details each clock source and its usage.
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Table 111. Oscillator Configuration and Selection Clock Source Internal Precision RC Oscillator Characteristics * 32.8 KHz or 5.53 MHz * High accuracy when trimmed * No external components required * 32 KHz to 20 MHz * Very high accuracy (dependent on crystal or resonator used) * Requires external components Required Setup * Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator at either 5.53 MHz or 32.8 KHz * Configure Flash option bits for correct external oscillator mode * Unlock and write OSCCTL to enable crystal oscillator, wait for it to stabilize and select as system clock (if the XTLDIS option bit has been deasserted, no waiting is required) * Configure Flash option bits for correct external oscillator mode * Unlock and write OSCCTL to enable crystal oscillator and select as system clock * Write GPIO registers to configure PB3 pin for external clock function * Unlock and write OSCCTL to select external system clock * Apply external clock signal to GPIO
External Crystal/ Resonator
External RC Oscillator
* 32 KHz to 4 MHz * Accuracy dependent on external components
External Clock Drive
* 0 to 20 MHz * Accuracy dependent on external clock source
Internal Watchdog Timer Oscillator
* Enable WDT if not enabled and wait * 10 KHz nominal * Low accuracy; no external components until WDT Oscillator is operating. * Unlock and write Oscillator Control required Register (OSCCTL) to enable and * Low power consumption select oscillator
Caution: Unintentional accesses to the oscillator control register can actually stop the chip by switching to a non-functioning oscillator. To prevent this condition, the oscillator control block employs a register unlocking/locking scheme. OSC Control Register Unlocking/Locking To write the oscillator control register, unlock it by making two writes to the OSCCTL register with the values E7H followed by 18H. A third write to the OSCCTL register changes the value of the actual register and returns the register to a locked state. Any other sequence of oscillator control register writes has no effect. The values written to unlock the register must be ordered correctly, but are not necessarily consecutive. It is possible to write to or read from other registers within the unlocking/locking operation.
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When selecting a new clock source, the system clock oscillator failure detection circuitry and the Watch-Dog Timer oscillator failure circuitry must be disabled. If SOFEN and WOFEN are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. The Failure detection circuitry can be enabled anytime after a successful write of OSCSEL in the OSCCTL register. The internal precision oscillator is enabled by default. If the user code changes to a different oscillator, it may be appropriate to disable the IPO for power savings. Disabling the IPO does not occur automatically.
Clock Failure Detection and Recovery
System Clock Oscillator Failure The Z8F04xA family devices can generate non-maskable interrupt-like events when the primary oscillator fails. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the Watch-Dog Timer oscillator to drive the system clock. The Watch-Dog Timer oscillator must be enabled to allow the recovery. Although this oscillator runs at a much slower speed than the original system clock, the CPU continues to operate, allowing execution of a clock failure vector and software routines that either remedy the oscillator failure or issue a failure alert. This automatic switch-over is not available if the Watch-Dog Timer is selected as the system clock oscillator. It is also unavailable if the Watch-Dog Timer oscillator is disabled, though it is not necessary to enable the Watch-Dog Timer reset function outlined in the Watch-Dog Timer chapter of this document on page 83. The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1KHz 50%. If an external signal is selected as the system oscillator, it is possible that a very slow but non-failing clock can generate a failure condition. Under these conditions, do not enable the clock failure circuitry (SOFEN must be deasserted in the OSCCTL register). Watch-Dog Timer Failure In the event of a Watch-Dog Timer oscillator failure, a similar non-maskable interrupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no longer possible to detect a primary oscillator failure. The failure detection circuitry does not function if the WatchDog Timer is used as the system clock oscillator or if the Watch-Dog Timer oscillator has been disabled. For either of these cases, it is necessary to disable the detection circuitry by deasserting the WDFEN bit of the OSCCTL register. The Watch-Dog Timer oscillator failure detection circuit counts system clocks while looking for a Watch-Dog Timer clock. The logic counts 8004 system clock cycles before determining that a failure has occurred. The system clock rate determines the speed at which
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the Watch-Dog Timer failure can be detected. A very slow system clock results in very slow detection times. Caution: It is possible to disable the clock failure detection circuitry as well as all functioning clock sources. In this case, the Z8 Encore! XP(R) 4K Series device ceases functioning and can only be recovered by Power-On-Reset.
Oscillator Control Register Definitions
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes the system clock. The Oscillator Control Register must be unlocked before writing. Writing the two step sequence E7H followed by 18H to the Oscillator Control Register unlocks it. The register is locked at successful completion of a register write to the OSCCTL.
Table 112. Oscillator Control Register (OSCCTL) BITS FIELD RESET R/W ADDR 7 INTEN 1 R/W 6 XTLEN 0 R/W 5 WDTEN 1 R/W 4 SOFEN 0 R/W F86H 3 WDFEN 0 R/W 0 R/W 2 1 SCKSEL 0 R/W 0 R/W 0
INTEN--Internal Precision Oscillator Enable 1 = Internal precision oscillator is enabled 0 = Internal precision oscillator is disabled XTLEN--Crystal Oscillator Enable; this setting overrides the GPIO register control for PA0 and PA1 1 = Crystal oscillator is enabled 0 = Crystal oscillator is disabled WDTEN--Watchdog Timer Oscillator Enable 1 = Watch-Dog Timer oscillator is enabled 0 = Watch-Dog Timer oscillator is disabled SOFEN--System Clock Oscillator Failure Detection Enable 1 = Failure detection and recovery of system clock oscillator is enabled 0 = Failure detection and recovery of system clock oscillator is disabled
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WDFEN--Watchdog Timer Oscillator Failure Detection Enable 1 = Failure detection of Watch-Dog Timer oscillator is enabled 0 = Failure detection of Watch-Dog Timer oscillator is disabled SCKSEL--System Clock Oscillator Select 000 = Internal precision oscillator functions as system clock at 5.53 MHz 001 = Internal precision oscillator functions as system clock at 32 KHz 010 = Crystal oscillator or external RC oscillator functions as system clock 011 = Watch-Dog Timer oscillator functions as system 100 = External clock signal on PB3 functions as system clock 101 = Reserved 110 = Reserved 111 = Reserved
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Crystal Oscillator
Overview
The products in the Z8 Encore! XP(R) 4K Series contain an on-chip crystal oscillator for use with external crystals with 32 KHz to 20 MHz frequencies. In addition, the oscillator supports external RC networks with oscillation frequencies up to 4 MHz or ceramic resonators with frequencies up to 8MHz. The on-chip crystal oscillator can be used to generate the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32 KHz-20 MHz). If an external clock generator is used, the XOUT pin must be left unconnected. The Z8 Encore! XP(R) 4K Series products do not contain an internal clock divider. The frequency of the signal on the XIN input pin determines the frequency of the system clock. Note: Although the XIN pin can be used as an input for an external clock generator, the CLKIN pin is better suited for such use (See System Clock Selection on page 180.)
Operating Modes
The Z8 Encore! XP(R) 4K Series products support four oscillator modes:
* * * *
Minimum power for use with very low frequency crystals (32 KHz-1 MHz) Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz to 8 MHz) Maximum power for use with high frequency crystals (8 MHz to 20 MHz) On-chip oscillator configured for use with external RC networks (<4 MHz)
The oscillator mode is selected using user-programmable Flash Option Bits. Please refer to the chapter Flash Option Bits on page 148 for information.
Crystal Oscillator Operation
The Flash Option bit XTLDIS controls whether the crystal oscillator is enabled during reset. The crystal may later be disabled after reset if a new oscillator has been selected as the system clock. If the crystal is manually enabled after reset through the OSCCTL register, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabilize. After this, the crystal oscillator may be selected as the system clock.
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Note:
The stabilization time will vary depending on the crystal or resonator used, as well as on the feedback network. See Table 114 for transconductance values to compute oscillator stabilization times. Figure 27 illustrates a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20 MHz. Recommended 20 MHz crystal specifications are provided in Table 113. Resistor R1 is optional and limits total power dissipation by the crystal. Printed circuit board layout must add no more than 4 pF of stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
Crystal
C1 = 15pF
C2 = 15pF
Figure 27.Recommended 20 MHz Crystal Oscillator Configuration
Table 113. Recommended Crystal Oscillator Specifications Parameter Frequency Resonance Mode Series Resistance (RS) Value 20 Parallel Fundamental 60 W Maximum Units MHz Comments
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Table 113. Recommended Crystal Oscillator Specifications Parameter Load Capacitance (CL) Shunt Capacitance (C0) Drive Level Value 30 7 1 Units pF pF mW Comments Maximum Maximum Maximum
Table 114. Transconductance Values for Low, Medium, and High Gain Operating Modes Transconductance (mA/V) Use this range for calculations 0.02 0.84 1.1 0.04 1.7 2.3 0.09 3.1 4.2
Mode Low Gain (see Note)
Crystal Frequence Range 32 KHz - 1 MHz
Function Low Power/Frequency Applications Medium Power/Frequency Applications High Power/Frequency Applications
Medium Gain 0.5 MHz - 10 MHz (see Note) High Gain (see Note) 8 MHz - 20 MHz
Note: * Printed circuit board layout should not add more than 4 pF of stray capacitance to either XIN or XOUT pins. if no Oscillation occurs, reduce the values of the capacitors C1 and C2 to decrease the loading.
Oscillator Operation with an External RC Network
Figure 28 illustrates a recommended configuration for connection with an external resistor-capacitor (RC) network.
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VDD
R
XIN
C
Figure 28.Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45 K is recommended for oscillator operation with an external RC network. The minimum resistance value to ensure operation is 40 K. The typical oscillator frequency can be estimated from the values of the resistor (R in K) and capacitor (C in pF) elements using the following equation:
1 x10 Oscillator Frequency (kHz) = --------------------------------------------------------( 0.4 x R x C ) + ( 4 x C )
Figure 29 illustrates the typical (3.3 V and 250C) oscillator frequency as a function of the capacitor (C in pF) employed in the RC network assuming a 45 K external resistor. For very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed circuit board should be included in the estimation of the oscillator frequency. It is possible to operate the RC oscillator using only the parasitic capacitance of the package and printed circuit board. To minimize sensitivity to external parasitics, external capacitance values in excess of 20 pF are recommended.
6
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4000 3750 3500 3250 3000 2750 2500 Frequency (kHz) 2250 2000 1750 1500 1250 1000 750 500 250 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C (pF)
Figure 29.Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45KOhm Resistor
Caution:
When using the external RC oscillator mode, the oscillator can stop oscillating if the power supply drops below 2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator resumes oscillation when the supply voltage exceeds 2.7V.
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Internal Precision Oscillator
Overview
The internal precision oscillator (IPO) is designed for use without external components. The user can either manually trim the oscillator for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53 MHz frequency. IPO features include:
* * * * Operation
On-chip RC oscillator that does not require external components Output frequency of either 5.53 MHz or 32.8 KHz (contains both a fast and a slow mode) Trimmed through Flash option bits with user override Elimination of crystals or ceramic resonators in applications where very high timing accuracy is not required.
An 8-bit trimming register, incorporated into the design, compensates for absolute variation of oscillator frequency. Once trimmed the oscillator frequency is stable and does not require subsequent calibration. Trimming is performed during manufacturing and is not necessary for the user to repeat unless a frequency other than 5.53 MHz (fast mode) or 32.8 KHz (slow mode) is required. This trimming is done at +30C and a supply voltage of 3.3 V, so accuracy of this operating point will be optimal. If not used, the IPO can be disabled by the Oscillator Control Register (page 183). By default, the oscillator frequency is set by the factory trim value stored in the write-protected flash information page. However, the user code can override these trim values as described in Trim Bit Address Space on page 153. Select one of two frequencies for the oscillator: 5.53 MHz and 32.8 KHz, using the OSCSEL bits in the Oscillator Control on page 180.
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eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called statements. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label identifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine language program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example
JP START START:
; Everything after the semicolon is a comment. ; A label called "START". The first instruction (JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data ; value 01H, is the source. The value 01H is written into the ; Register at address 234H.
LD R4, R7
LD 234H, #%01
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Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as `destination, source'. After assembly, the object code usually has the operands in the order 'source, destination', but ordering is opcode-dependent. The following instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is:
Table 115. Assembly Language Syntax Example 1 Assembly Language Code Object Code ADD 04 43H, 08 08H 43 (ADD dst, src) (OPC src, dst)
Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0-255 or, using Escaped Mode Addressing, a Working Register R0-R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is:
Table 116. Assembly Language Syntax Example 2 Assembly Language Code Object Code ADD 04 43H, E8 R8 43 (ADD dst, src) (OPC src, dst)
See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by a notational shorthand that is described in Table 117.
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.
Table 117. Notational Shorthand Notation Description b cc DA ER IM Ir IR Irr IRR p r R RA Bit Condition Code Direct Address Extended Addressing Register Immediate Data Indirect Working Register Indirect Register Indirect Working Register Pair Indirect Register Pair Polarity Working Register Register Relative Address Operand Range b -- Addrs Reg #Data @Rn @Reg @RRp @Reg p Rn Reg X b represents a value from 0 to 7 (000B to 111B). See Condition Codes overview in the eZ8 CPU User Manual. Addrs. represents a number in the range of 0000H to FFFFH Reg. represents a number in the range of 000H to FFFH Data is a number between 00H to FFH n = 0 -15 Reg. represents a number in the range of 00H to FFH p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range 00H to FEH Polarity is a single bit binary value of either 0B or 1B. n = 0 - 15 Reg. represents a number in the range of 00H to FFH X represents an index in the range of +127 to - 128 which is an offset relative to the address of the next instruction p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range of 00H to FEH Vector represents a number in the range of 00H to FFH The register or register pair to be indexed is offset by the signed Index value (#Index) in a +127 to -128 range.
rr RR Vector X
Working Register Pair Register Pair Vector Address Indexed
RRp Reg Vector #Index
Table 118 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections.
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Table 118. Additional Symbols Symbol dst src @ SP PC FLAGS RP # B % H Definition Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix
Assignment of a value is indicated by an arrow. For example, dst dst + src indicates the source data is added to the destination data and the result is stored in the destination location.
eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
* * * * * * * *
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Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift
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Tables 119 through 126 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as 'src', the destination operand is 'dst' and a condition code is 'cc'.
Table 119. Arithmetic Instructions Mnemonic ADC ADCX ADD ADDX CP CPC CPCX CPX DA DEC DECW INC INCW MULT SBC SBCX SUB SUBX Operands dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst dst dst dst dst dst dst, src dst, src dst, src dst, src Instruction Add with Carry Add with Carry using Extended Addressing Add Add using Extended Addressing Compare Compare with Carry Compare with Carry using Extended Addressing Compare using Extended Addressing Decimal Adjust Decrement Decrement Word Increment Increment Word Multiply Subtract with Carry Subtract with Carry using Extended Addressing Subtract Subtract using Extended Addressing
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Table 120. Bit Manipulation Instructions Mnemonic BCLR BIT BSET BSWAP CCF RCF SCF TCM TCMX TM TMX Operands bit, dst p, bit, dst bit, dst dst -- -- -- dst, src dst, src dst, src dst, src Instruction Bit Clear Bit Set or Clear Bit Set Bit Swap Complement Carry Flag Reset Carry Flag Set Carry Flag Test Complement Under Mask Test Complement Under Mask using Extended Addressing Test Under Mask Test Under Mask using Extended Addressing
Table 121. Block Transfer Instructions Mnemonic LDCI LDEI Operands dst, src dst, src Instruction Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory and Auto-Increment Addresses
Table 122. CPU Control Instructions Mnemonic ATM CCF DI EI HALT NOP RCF SCF SRP Operands -- -- -- -- -- -- -- -- src Instruction Atomic Execution Complement Carry Flag Disable Interrupts Enable Interrupts Halt Mode No Operation Reset Carry Flag Set Carry Flag Set Register Pointer
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Table 122. CPU Control Instructions Mnemonic STOP WDT Operands -- -- Instruction STOP Mode Watch-Dog Timer Refresh
Table 123. Load Instructions Mnemonic CLR LD LDC LDCI LDE LDEI LDWX LDX LEA POP POPX PUSH PUSHX Operands Instruction dst dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst dst src src Clear Load Load Constant to/from Program Memory Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory Load External Data to/from Data Memory and Auto-Increment Addresses Load Word using Extended Addressing Load using Extended Addressing Pop Pop using Extended Addressing Push Push using Extended Addressing
dst, X(src) Load Effective Address
Table 124. Logical Instructions Mnemonic Operands Instruction AND ANDX COM OR ORX dst, src dst, src dst dst, src dst, src Logical AND Logical AND using Extended Addressing Complement Logical OR Logical OR using Extended Addressing
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Table 124. Logical Instructions Mnemonic Operands Instruction XOR XORX dst, src dst, src Logical Exclusive OR Logical Exclusive OR using Extended Addressing
Table 125. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET JP JP cc JR JR cc RET TRAP Operands -- bit, src, DA bit, src, DA dst dst, src, RA -- dst dst DA DA -- vector Instruction On-Chip Debugger Break Bit Test and Jump if Non-Zero Bit Test and Jump if Zero Call Procedure Decrement and Jump Non-Zero Interrupt Return Jump Jump Conditional Jump Relative Jump Relative Conditional Return Software Trap
p, bit, src, DA Bit Test and Jump
Table 126. Rotate and Shift Instructions Mnemonic BSWAP RL RLC RR RRC SRA Operands dst dst dst dst dst dst Instruction Bit Swap Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Shift Right Arithmetic
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Table 126. Rotate and Shift Instructions Mnemonic SRL SWAP Operands dst dst Instruction Shift Right Logical Swap Nibbles
eZ8 CPU Instruction Summary
Table 127 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.
.
Table 127. eZ8 CPU Instruction Summary Assembly Mnemonic
ADC dst, src Address Mode Opcode(s) (Hex) C 12 13 14 15 16 17 18 19 02 03 04 05 06 07 08 09 * * * * 0 * * * * * 0 * * * * * 0 * * Flags Z * S * V * D 0 Fetch Instr. H Cycles Cycles * 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3
Symbolic Operation
dst dst + src + C
dst r r R R R IR
src r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM
ADCX dst, src
dst dst + src + C
ER ER
ADD dst, src
dst dst + src
r r R R R IR
ADDX dst, src
dst dst + src
ER ER
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
AND dst, src Address Mode Opcode(s) (Hex) C 52 53 54 55 56 57 58 59 2F - - - - - - - * * 0 - - - Flags Z * S * V 0 D - Fetch Instr. H Cycles Cycles - 2 2 3 3 3 3 4 4 1 3 4 3 4 3 4 3 3 2
Symbolic Operation
dst dst AND src
dst r r R R R IR
src r Ir R IR IM IM ER IM
ANDX dst, src
dst dst AND src
ER ER
ATM
Block all interrupt and DMA requests during execution of the next 3 instructions dst[bit] 0 dst[bit] p Debugger Break dst[bit] 1 dst[7:0] dst[0:7] r R r Ir r Ir r Ir IRR DA r r
BCLR bit, dst BIT p, bit, dst BRK BSET bit, dst BSWAP dst
E2 E2 00 E2 D5 F6 F7 F6 F7 F6 F7 D4 D6 EF
- - - - X -
* * - * * -
* * - * * -
0 0 - 0 0 -
- - - - - -
- - - - - -
2 2 1 2 2 3 3
2 2 1 2 2 3 4 3 4 3 4 6 3 2 2 3
BTJ p, bit, src, dst if src[bit] = p PC PC + X BTJNZ bit, src, dst if src[bit] = 1 PC PC + X BTJZ bit, src, dst if src[bit] = 0 PC PC + X SP SP -2 @SP PC PC dst C ~C dst 00H R IR Flags Notation:
-
-
-
-
-
-
3 3
-
-
-
-
-
-
3 3
CALL dst
-
-
-
-
-
-
2 3
CCF CLR dst
* -
- -
- -
- -
- -
--
1 2 2
B0 B1
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
COM dst Address Mode Opcode(s) (Hex) C 60 61 r Ir R IR IM IM r Ir R IR IM IM ER IM ER IM A2 A3 A4 A5 A6 A7 1F A2 1F A3 1F A4 1F A5 1F A6 1F A7 1F A8 1F A9 A8 A9 40 41 30 31 80 81 8F r 0A-FA - - - - - - - - - - - - - * * * - - - * * * - - * * * X - - * * * * - - * * * * - - * * * * - - * * * * - - - Flags Z * S * V 0 D - Fetch Instr. H Cycles Cycles - 2 2 2 2 3 3 3 3 3 3 4 4 4 4 5 5 4 4 2 2 2 2 2 2 1 2 2 3 3 4 3 4 3 4 3 4 3 4 3 4 3 3 3 3 2 3 2 3 5 6 2 3
Symbolic Operation
dst ~dst
dst R IR
src
CP dst, src
dst - src
r r R R R IR
CPC dst, src
dst - src - C
r r R R R IR
CPCX dst, src
dst - src - C
ER ER
CPX dst, src
dst - src
ER ER
DA dst
dst DA(dst)
R IR
DEC dst
dst dst - 1
R IR
DECW dst
dst dst - 1
RR IRR
DI DJNZ dst, RA
IRQCTL[7] 0 dst dst - 1 if dst 0 PC PC + X IRQCTL[7] 1
EI Flags Notation:
9F
-
-
-
-
-
-
1
2
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
HALT INC dst Address Mode Opcode(s) (Hex) C 7F R IR r INCW dst dst dst + 1 RR IRR IRET FLAGS @SP SP SP + 1 PC @SP SP SP + 2 IRQCTL[7] 1 PC dst DA IRR JP cc, dst JR dst JR cc, dst LD dst, rc if cc is true PC dst PC PC + X if cc is true PC PC + X dst src DA DA DA r r X(r) r R R R IR Ir IR Flags Notation: IM X(r) r Ir R IR IM IM r R 20 21 0E-FE A0 A1 BF * * * * * * - * * * - - - - Flags Z - * S - * V - - D - - Fetch Instr. H Cycles Cycles - - 1 2 2 1 2 2 1 2 2 3 2 5 6 5
Symbolic Operation
Halt Mode dst dst + 1
dst
src
JP dst
8D C4 0D-FD 8B 0B-FB 0C-FC C7 D7 E3 E4 E5 E6 E7 F3 F5
-
-
-
-
-
-
3 2
2 3 2 2 2 2 3 4 3 2 4 2 3 3 3
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
3 2 2 2 3 3 2 3 3 3 3 2 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
LDC dst, src Address Mode Opcode(s) (Hex) C C2 C5 D2 C3 D3 82 92 83 93 1FE8 84 85 86 87 88 89 94 95 96 97 E8 E9 98 99 F4 0F - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Flags Z - S - V - D - Fetch Instr. H Cycles Cycles - 2 2 2 2 2 2 2 2 2 5 3 3 3 3 3 3 3 3 3 3 4 4 3 3 2 1 5 9 5 9 9 5 5 9 9 4 2 3 4 5 4 4 2 3 4 5 2 2 3 5 8 2
Symbolic Operation
dst src
dst r Ir Irr
src Irr Irr r Irr Ir Irr r Irr Ir ER ER ER IRR IRR X(rr) r r Ir R IR ER IM X(r) X(rr)
LDCI dst, src
dst src rr+1 rr rr + 1 dst src
Ir Irr r Irr
LDE dst, src
LDEI dst, src
dst src rr+1 rr rr + 1 dst src dst src
Ir Irr ER r Ir R IR r X(rr) ER ER IRR IRR ER ER
LDWX dst, src LDX dst, src
LEA dst, X(src)
dst src + X
r rr
MULT dst NOP Flags Notation:
dst[15:0] dst[15:8] * dst[7:0] No operation
RR
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
OR dst, src Address Mode Opcode(s) (Hex) C 42 43 44 45 46 47 48 49 50 51 D8 70 71 IF70 - - - - - - - - - - - - - - - - - - - * * 0 - - - Flags Z * S * V 0 D - Fetch Instr. H Cycles Cycles - 2 2 3 3 3 3 4 4 2 2 3 2 2 3 3 4 3 4 3 4 3 3 2 3 2 2 3 2
Symbolic Operation
dst dst OR src
dst r r R R R IR
src r Ir R IR IM IM ER IM
ORX dst, src
dst dst OR src
ER ER
POP dst
dst @SP SP SP + 1 dst @SP SP SP + 1 SP SP - 1 @SP src
R IR ER R IR IM
POPX dst PUSH src
PUSHX src RCF RET RL dst
SP SP - 1 @SP src C0 PC @SP SP SP + 2
ER
C8 CF AF
- 0 - *
- - - *
- - - *
- - - *
- - - -
- - - -
3 1 1 2 2
2 2 4 2 3
R
C D7 D6 D5 D4 D3 D2 D1 D0 dst
90 91
IR
RLC dst
C D7 D6 D5 D4 D3 D2 D1 D0 dst
R IR
10 11
*
*
*
*
-
-
2 2
2 3
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
RR dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
Address Mode
Symbolic Operation
dst R IR
src
Opcode(s) (Hex) C E0 E1 *
Flags Z * S * V * D -
Fetch Instr. H Cycles Cycles - 2 2 2 3
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
R IR r r R R R IR r Ir R IR IM IM ER IM
C0 C1 32 33 34 35 36 37 38 39 DF
*
*
*
*
-
-
2 2
2 3 3 4 3 4 3 4 3 3 2 2 3
SBC dst, src
dst dst - src - C
*
*
*
*
1
*
2 2 3 3 3 3
SBCX dst, src
dst dst - src - C
ER ER
*
*
*
*
1
*
4 4
SCF SRA dst
C1 R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
1 *
- *
- *
- 0
- -
- -
1 2 2
D0 D1
IR
SRL dst
0
D7 D6 D5 D4 D3 D2 D1 D0 dst
C
R IR IM
1F C0 1F C1 01 6F
*
*
0
*
-
-
3 3
2 3 2 2 3 4 3 4 3 4
SRP src STOP SUB dst, src
RP src STOP Mode dst dst - src r r R R R IR
- - *
- - *
- - *
- - *
- - 1
- - *
2 1 2 2 3 3 3 3
r Ir R IR IM IM
22 23 24 25 26 27
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
SUBX dst, src Address Mode Opcode(s) (Hex) C 28 29 F0 F1 r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM Vector 62 63 64 65 66 67 68 69 72 73 74 75 76 77 78 79 F2 - - - - - - - * * 0 - - - * * 0 - - - * * 0 - - - * * 0 - - X * * X - - * Flags Z * S * V * D 1 Fetch Instr. H Cycles Cycles * 4 4 2 2 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 2 3 3 2 3 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3 6
Symbolic Operation
dst dst - src
dst ER ER
src ER IM
SWAP dst
dst[7:4] dst[3:0]
R IR
TCM dst, src
(NOT dst) AND src
r r R R R IR
TCMX dst, src
TM dst, src
(NOT dst) AND src
dst AND src
ER ER r r R R R IR
TMX dst, src
dst AND src
ER ER
TRAP Vector
SP SP - 2 @SP PC SP SP - 1 @SP FLAGS PC @Vector
WDT Flags Notation:
5F * = Value is a function of the result of the operation. - = Unaffected X = Undefined
-
-
-
-
-
-
1
2
0 = Reset to 0 1 = Set to 1
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Table 127. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic
XOR dst, src Address Mode Opcode(s) (Hex) C B2 B3 B4 B5 B6 B7 B8 B9 - * * 0 - - - Flags Z * S * V 0 D - Fetch Instr. H Cycles Cycles - 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3
Symbolic Operation
dst dst XOR src
dst r r R R R IR
src r Ir R IR IM IM ER IM
XORX dst, src
dst dst XOR src
ER ER
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 30. Figures 31 and Figure 32 provide information about each of the eZ8 CPU instructions. Table 128 lists Opcode Map abbreviations.
Opcode Lower Nibble Fetch Cycles 4 3.3 Opcode Upper Nibble A CP R2,R1 Instruction Cycles
First Operand After Assembly
Second Operand After Assembly
Figure 30.Opcode Map Cell Description
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Table 128. Opcode Map Abbreviations Abbreviation b cc X DA ER IM Ir IR Irr Description Bit position Condition code 8-bit signed index or displacement Destination address Extended Addressing register Immediate data value Indirect Working Register Indirect register Indirect Working Register Pair Abbreviation IRR p r R r1, R1, Ir1, Irr1, IR1, rr1, RR1, IRR1, ER1 r2, R2, Ir2, Irr2, IR2, rr2, RR2, IRR2, ER2 RA rr RR Description Indirect Register Pair Polarity (0 or 1) 4-bit Working Register 8-bit register Destination address Source address Relative Working Register Pair Register Pair
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0
1.1
1
2.2
2
2.3
3
2.4
4
3.3
5
3.4
6
3.3
Lower Nibble (Hex) 7 8 9
3.4 4.3 4.3
A
2.3 r1,X
B
2.2
C
2.2
D
3.2
E
1.2
F
1.2
0 1 2 3 4 5 6 Upper Nibble (Hex) 7 8 9 A B C D E F
BRK
2.2
SRP
IM 2.3
ADD
r1,r2 2.3
ADD
r1,Ir2 2.4
ADD
R2,R1 3.3
ADD
IR2,R1 3.4
ADD
R1,IM 3.3
ADD
3.4
ADDX ADDX DJNZ
4.3 4.3
JR
cc,X
LD
r1,IM
JP
cc,DA
INC
r1
NOP
See 2nd Opcode Map 1, 2 ATM
IR1,IM ER2,ER1 IM,ER1
RLC
R1 2.2
RLC
IR1 2.3
ADC
r1,r2 2.3
ADC
r1,Ir2 2.4
ADC
R2,R1 3.3
ADC
IR2,R1 3.4
ADC
R1,IM 3.3
ADC
3.4
ADCX ADCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
INC
R1 2.2
INC
IR1 2.3
SUB
r1,r2 2.3
SUB
r1,Ir2 2.4
SUB
R2,R1 3.3
SUB
IR2,R1 3.4
SUB
R1,IM 3.3
SUB
3.4
SUBX SUBX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
DEC
R1 2.2
DEC
IR1 2.3
SBC
r1,r2 2.3
SBC
r1,Ir2 2.4
SBC
R2,R1 3.3
SBC
IR2,R1 3.4
SBC
R1,IM 3.3
SBC
3.4
SBCX SBCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
DA
R1 2.2
DA
IR1 2.3
OR
r1,r2 2.3
OR
r1,Ir2 2.4
OR
R2,R1 3.3
OR
IR2,R1 3.4
OR
R1,IM 3.3
OR
3.4
ORX
4.3
ORX
4.3 1.2
IR1,IM ER2,ER1 IM,ER1
POP
R1 2.2
POP
IR1 2.3
AND
r1,r2 2.3
AND
r1,Ir2 2.4
AND
R2,R1 3.3
AND
IR2,R1 3.4
AND
R1,IM 3.3
AND
3.4
ANDX ANDX
4.3 4.3
WDT
1.2
IR1,IM ER2,ER1 IM,ER1
COM
R1 2.2 R2 2.5 RR1 2.2
COM
IR1 2.3 IR2 2.6 IRR1 2.3
TCM
r1,r2 2.3
TCM
r1,Ir2 2.4
TCM
R2,R1 3.3
TCM
IR2,R1 3.4
TCM
R1,IM 3.3
TCM
3.4
TCMX TCMX
4.3 4.3
STOP
1.2
IR1,IM ER2,ER1 IM,ER1
PUSH PUSH DECW DECW RL
R1 2.5 RR1 2.2
TM
r1,r2 2.5
TM
r1,Ir2 2.9
TM
R2,R1 3.2
TM
IR2,R1 3.3
TM
R1,IM 3.4
TM
3.5
TMX
3.4
TMX
3.4
HALT
1.2
IR1,IM ER2,ER1 IM,ER1
LDE
r1,Irr2 2.5
LDEI
Ir1,Irr2 2.9
LDX
r1,ER2 3.2
LDX
3.3
LDX
3.4
LDX
3.5
LDX
3.3
LDX
rr1,r2,X 3.5
DI
1.2
Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X
RL
IR1 2.6 IRR1 2.3
LDE
r2,Irr1 2.3
LDEI
Ir2,Irr1 2.4
LDX
r2,ER1 3.3
LDX
3.4
LDX
3.3
LDX
3.4
LEA
4.3
LEA
rr1,rr2,X 4.3
EI
1.4
Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X
INCW INCW CLR
R1 2.2
CP
r1,r2 2.3
CP
r1,Ir2 2.4
CP
R2,R1 3.3
CP
IR2,R1 3.4
CP
R1,IM 3.3
CP
3.4
CPX
4.3
CPX
4.3
RET
1.5
IR1,IM ER2,ER1 IM,ER1
CLR
IR1 2.3
XOR
r1,r2 2.5
XOR
r1,Ir2 2.9
XOR
R2,R1 2.3
XOR
IR2,R1 2.9
XOR
R1,IM
XOR
3.4
XORX XORX
3.2
IRET
1.2
IR1,IM ER2,ER1 IM,ER1
RRC
R1 2.2
RRC
IR1 2.3
LDC
r1,Irr2 2.5
LDCI
Ir1,Irr2 2.9
JP
IRR1 2.6 IRR1 3.2
LDC
Ir1,Irr2 2.2 R1 3.3 3.3 DA 3.2
LD
r1,r2,X 3.4
PUSHX
ER2 3.2
RCF
1.2
SRA
R1 2.2
SRA
IR1 2.3
LDC
r2,Irr1 2.2
LDCI
Ir2,Irr1 2.3
CALL BSWAP CALL LD
R2,R1 2.8
LD
r2,r1,X 3.3
POPX
ER1 4.2 4.2
SCF
1.2
RR
R1 2.2 R1
RR
IR1 2.3 IR1
BIT
p,b,r1 2.6 Vector
LD
r1,Ir2 2.3
LD
IR2,R1 3.3
LD
R1,IM 3.3
LD
3.4
LDX
LDX
CCF
IR1,IM ER2,ER1 IM,ER1
SWAP SWAP TRAP
LD
Ir1,r2
MULT
RR1
LD
R2,IR1
BTJ
BTJ
p,b,r1,X p,b,Ir1,X
Figure 31.First Opcode Map
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0 0 1 2 3 4 5 6 Upper Nibble (Hex) 7 8 9 PUSH
IM 3, 2
1
2
3
4
5
6
Lower Nibble (Hex) 7 8 9
A
B
C
D
E
F
3.3
3.4
4.3
4.4
4.3
4.4
5.3
5.3
A B
3.2 3.3
CPC
r1,r2
CPC
r1,Ir2
CPC
R2,R1
CPC
IR2,R1
CPC
R1,IM
CPC
CPCX CPCX
IR1,IM ER2,ER1 IM,ER1
C D
SRL
R1
SRL
IR1
5, 4
E F
LDWX
ER2,ER1
Figure 32.Second Opcode Map after 1FH
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Electrical Characteristics
The data in this chapter is pre-qualification and pre-characterization and is subject to change. Additional electrical characteristics may be found in the individual chapters.
Absolute Maximum Ratings
Stresses greater than those listed in Table 129 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS).
Table 129. Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin
8-pin Packages Maximum Ratings at 0C to 70C
-40 -65 -0.3 -0.3 -5 -25
+105 +150 +5.5 +3.6 +5 +25
C C V V A mA 1
Total power dissipation Maximum current into VDD or out of VSS
20-pin Packages Maximum Ratings at 0C to 70C
220 60
mW mA
Total power dissipation Maximum current into VDD or out of VSS
28-pin Packages Maximum Ratings at 0C to 70C
430 120
mW mA
Total power dissipation Maximum current into VDD or out of VSS Operating temperature is specified in DC Characteristics
450 125
mW mA
1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Port B[5:0], Port C[2:0]) and pins supporting the crystal oscillator (PA0 and PA1). On the 8-pin packages, this applies to all pins but VDD.
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DC Characteristics
Table 130 lists the DC characteristics of the Z8 Encore! XP(R) 4K Series products. All voltages are referenced to VSS, the primary system ground.
Table 130. DC Characteristics
TA = -40C to +105C (unless otherwise specified) Symbol Parameter Minimum Typical Maximum Units Conditions
VDD VIL1 VIH1
Supply Voltage Low Level Input Voltage High Level Input Voltage
2.7 -0.3 2.0
- - -
3.6 0.3*VDD 5.5
V V V For all input pins without analog or oscillator function. For all signal pins on the 8-pin devices. Programmable pull-ups must also be disabled. For those pins with analog or oscillator function (20-/28-pin devices only), or when programmable pull-ups are enabled. IOL = 2mA; VDD = 3.0V High Output Drive disabled. IOH = -2mA; VDD = 3.0V High Output Drive disabled. IOL = 20mA; VDD = 3.3V High Output Drive enabled. IOH = -20mA; VDD = 3.3V High Output Drive enabled.
VIH2
High Level Input Voltage
2.0
-
VDD+0.3
V
VOL1 VOH1 VOL2 VOH2 IIH IIL ILED
Low Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Output Voltage Input Leakage Current Input Leakage Current Controlled Current Drive
- 2.4 - 2.4 - - 1.8 2.8 7.8 12
- - - - +0.002 +0.007 3 7 13 20 8.0
2
0.4 - 0.6 - +5 +5 4.5 10.5 19.5 30 - -
V V V V A A
mA {AFS2,AFS1} = {0,0} mA {AFS2,AFS1} = {0,1} mA {AFS2,AFS1} = {1,0} mA {AFS2,AFS1} = {1,1} pF TBD pF TBD
CPAD CXIN
GPIO Port Pad Capacitance XIN Pad Capacitance
- -
8.02
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Table 130. DC Characteristics (Continued)
TA = -40C to +105C (unless otherwise specified) Symbol Parameter Minimum Typical Maximum Units Conditions
CXOUT IPU VRAM
XOUT Pad Capacitance Weak Pull-up Current RAM Data Retention Voltage
- 30 TBD
9.52 100
- 350
pF TBD A VDD = 3.0 - 3.6V V Voltage at which RAM will retain static values; no reading or writing is allowed.
1 2
This condition excludes all pins that have on-chip pull-ups, when driven Low. These values are provided for design guidance only and are not tested in production.
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Table 131. Power Consumption
VDD = 2.7V to 3.6V TA = 0C to +70C Symbol Parameter Minimum Typical1 Maximum Units Conditions
IDD Stop IDD Halt
Supply Current in STOP Mode Supply Current in HALT Mode (with all peripherals disabled)
1 4 520 1.9 3.3 4.2 4.9 6.5
A No peripherals enabled. All pins driven to VDD or VSS. A 32 kHz A 5.5 MHz mA 20 MHz mA 32 kHz mA 5.5 MHz mA 10 MHz mA 20 MHz A A 32 kHz A 4 MHz A 20 MHz mA A For 20-/28-pin devices (VBO only); See Note 2 For 8-pin devices; See Note 2 mA 32 kHz mA 5.5 MHz mA 10 MHz mA 20 MHz A See Note 2 A See Note 2 A Driving a high-impedance load
IDD
Supply Current in ACTIVE Mode
IDD WDT IDD XTAL
Watchdog Timer Supply Current Crystal Oscillator Supply Current
1 40 230 760 1.5 50
IDD IPO IDD VBO
Internal Precision Oscillator Supply Current Voltage Brown-Out and Low-Voltage Detect Supply Current Analog to Digital Converter Supply Current (with External Reference)
IDD ADC
2.8 3.0 3.2 3.5 0 100 2
IDD ADCRef ADC Internal Reference Supply Current IDD CMP IDD LPO Comparator supply Current Low-Power Operational Amplifier Supply Current
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Table 131. Power Consumption (Continued)
VDD = 2.7V to 3.6V TA = 0C to +70C Symbol Parameter Minimum Typical1 Maximum Units Conditions
IDD TS IDD BG
Temperature Sensor Supply Current Band Gap Supply Current
60 310
A See Note 2. A For 20-/28-pin devices For 8-pin devices
1 2
Typical conditions are defined as Vdd = 3.3V and +30C. For this block to operate, the bandgap circuit is automatically turned on and must be added to the total supply current. This bandgap current is only added once, regardless of how many peripherals are using it.
Figure 33 illustrates illustrates the typical current consumption while operating with all peripherals disabled, at 30C, versus the system clock frequency.
Typical Supply Current - Active Mode 10 8 IDD (mA) 6 4 2 0 0 5 10 Freq (MHz)
Figure 33. Typical Active Mode IDD Versus System Clock Frequency
VDD = 3.60V / 30C VDD = 3.30V / 30C VDD = 2.70V / 30C
15
20
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AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs.
Table 132. AC Characteristics
VDD = 2.7 to 3.6V TA = -40C to +105C (unless otherwise stated) Symbol Parameter Minimum Maximum Units Conditions
FSYSCLK System Clock Frequency
- 0.032768
20.0 20.0 20.0
MHz MHz MHz
Read-only from Flash memory Program or erasure of the Flash memory System clock frequencies below the crystal oscillator minimum require an external clock driver. TCLK = 1/Fsysclk TCLK = 50ns TCLK = 50ns TCLK = 50ns TCLK = 50ns
FXTAL
Crystal Oscillator Frequency
-
TXIN TXINH TXINL TXINR TXINF
System Clock Period System Clock High Time System Clock Low Time System Clock Rise Time System Clock Fall Time
50 20 20 - -
- 30 30 3 3
ns ns ns ns ns
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Table 133. Internal Precision Oscillator Electrical Characteristics
VDD = 2.7 to 3.6V TA = -40C to +105C (unless otherwise stated) Symbol Parameter Minimum Typical Maximum Units Conditions
FIPO FIPO FIPO TIPOST
Internal Precision Oscillator Frequency (High Speed) Internal Precision Oscillator Frequency (High Speed) Internal Precision Oscillator Frequency (Low Speed) Internal Precision Oscillator Startup Time 5.31 30.7
5.53 5.53 32.7 0.7 5.75 33.3 MHz KHz s
VDD = 3.3V TA = 30C
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On-Chip Peripheral AC and DC Electrical Characteristics
Table 134. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
TA = -40C to +105C Symbol Parameter Minimum Typical1 Maximum Units Conditions
VPOR VVBO
Power-On Reset Voltage Threshold Voltage Brown-Out Reset Voltage Threshold VPOR to VVBO hysteresis Starting VDD voltage to ensure valid Power-On Reset.
2.20 2.15
2.45 2.40 50
2.70 2.65 75 -
V V mV V
VDD = VPOR VDD = VVBO
-
VSS
TANA TPOR
Power-On Reset Analog Delay Power-On Reset Digital Delay Power-On Reset Digital Delay STOP Mode Recovery with crystal oscillator disabled STOP Mode Recovery with crystal oscillator enabled Voltage Brown-Out Pulse Rejection Period
-
50 16
-
s s
VDD > VPOR; TPOR Digital Reset delay follows TANA 66 Internal Precision Oscillator cycles + IPO startup time (TIPOST) 5000 Internal Precision Oscillator cycles 66 Internal Precision Oscillator cycles 5000 Internal Precision Oscillator cycles VDD < VVBO to generate a Reset.
TPOR TSMR
1 16
ms s
TSMR
1
ms
TVBO
-
0.10
10
-
-
100
s ms
TRAMP Time for VDD to transition from VSS to VPOR to ensure valid Reset TSMP Stop-Mode Recovery pin pulse rejection period
20
ns
For any SMR pin or for the Reset pin when it is asserted in STOP mode.
1 Data in the typical column is from characterization at 3.3V and 30C. These values are provided for design guidance only and are not tested in production.
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Table 135. Flash Memory Electrical Characteristics and Timing
VDD = 2.7 to 3.6V TA = -40C to +105C (unless otherwise stated) Parameter Minimum Typical Maximum Units Notes
Flash Byte Read Time Flash Byte Program Time Flash Page Erase Time Flash Mass Erase Time Writes to Single Address Before Next Erase Flash Row Program Time
100 20 10 200 - -
- - - - - -
- 40 - - 2 8
ns s ms ms
ms
Cumulative program time for single row cannot exceed limit before next erase. This parameter is only an issue when bypassing the Flash Controller.
Data Retention Endurance
100 10,000
- -
- -
years 25C cycles Program / erase cycles
Table 136. Watch-Dog Timer Electrical Characteristics and Timing
VDD = 2.7 - 3.6V TA = -40C to +105C (unless otherwise stated) Symbol Parameter Minimum Typical Maximum Units Conditions
FWDT
WDT Oscillator Frequency
5
10 100 100 100
15
KHz ms ms ms VDD = 3.3V; TA = 30C VDD = 2.7V to 3.6V TA = 0C to 70C VDD = 2.7V to 3.6V TA = -40C to +105C
TWDTCAL WDT Calibrated Timeout
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Table 137. Non Volatile Data Storage
VDD = 2.7 - 3.6V TA = -40C to +105C Parameter Minimum Typical Maximum Units Notes
NVDS Byte Read Time NVDS Byte Program Time Data Retention Endurance
34 0.171 100 160,000
- - - -
519 39.7 - -
s ms
With system clock at 20MHz With system clock at 20MHz
years 25C cycles Cumulative write cycles for entire memory
Table 138. Analog-to-Digital Converter Electrical Characteristics and Timing
VDD = 3.0 to 3.6V TA = 0C to +70C Symbol Parameter Minimum Typical Maximum Units Conditions
Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Offset Error with Calibration Absolute Accuracy with Calibration VREF Internal Reference Voltage
10 -1.0 -3.0 - - +1 +3 1.0 2.0 1.1 2.2 850
- 1.0 3.0
bits LSB3 LSB3 LSB3 LSB3 External VREF = 2.0V; RS 3.0K External VREF = 2.0V; RS 3.0K
1.2 2.4
V
REFSEL=01 REFSEL=10 When the internal reference is buffered and driven out to the VREF pin (REFOUT = 1)
RREFOUT Reference Buffer Ouput Impedance
Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time. 2 Devices are factory calibrated at VDD = 3.3V and TA = +30C, so the ADC is maximally accurate under these conditions. 3 LSBs are defined assuming 10-bit resolution. 4 The input impedance is inversely proportional to the system clock frequency.
1
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Table 138. Analog-to-Digital Converter Electrical Characteristics and Timing
VDD = 3.0 to 3.6V TA = 0C to +70C Symbol Parameter Minimum Typical Maximum Units Conditions
Single-Shot Conversion Time
-
5129
-
System All measurements but clock temperature sensor cycles Temperature sensor measurement
10258 Continuous Conversion Time - 256 -
System All measurements but clock temperature sensor cycles Temperature sensor measurement kHz As defined by -3dB point In unbuffered mode In buffered modes In unbuffered mode at 20MHz4 In buffered modes Unbuffered Mode Buffered Modes Note: these values define the range over which the ADC performs within spec; exceeding these values does not cause damage or instability; see DC Characteristics on page 213 for absolute pin voltage limits
512 Signal Input Bandwidth RS Zin Analog Source Impedance Input Impedance - - TBD 10 Vin Input Voltage Range 0 0.3 10 - 150 TBD VDD VDD-1.1 10 500
k k k M V V
Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time. 2 Devices are factory calibrated at VDD = 3.3V and TA = +30C, so the ADC is maximally accurate under these conditions. 3 LSBs are defined assuming 10-bit resolution. 4 The input impedance is inversely proportional to the system clock frequency.
1
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Table 139. Low Power Operational Amplifer Electrical Characteristics
VDD = 2.7 to 3.6V TA = -40C to +105C Symbol Parameter Minimum Typical Maximum Units Conditions
Av GBW PM VosLPO VosLPO
Open loop voltage gain Gain/Bandwidth product Phase Margin Input Offset Voltage Input Offset Voltage (Temperature Drift) -4
80 500 53 4 1 10
dB kHz deg mV V/C Over the range of -10C to +40C Assuming 13pF pin capacitance
Table 140. Comparator Electrical Characteristics
VDD = 2.7 to 3.6V TA = -40C to +105C Symbol Parameter Minimum Typical Maximum Units Conditions
VOS VCREF TPROP VHYS VIN
Input DC Offset Programmable Internal Reference Voltage Propagation Delay Input Hysteresis Input Voltage Range VSS
5 +5 +3 100 4 VDD-1
mV % % ns mV V 20-/28-pin devices 8-pin devices
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Table 141. Temperature Sensor Electrical Characteristics
VDD = 2.7 to 3.6V Symbol Parameter Minimum Typical Maximum Units Conditions
TAERR
Temperature Error
+1.5
C
Over the range +20C to +30C (as measured by ADC) Over the range +0C to +70C (as measured by ADC) Over the range -40C to +105C (as measured by ADC) Over the range -40C to +105C (as measured by comparator) Time required for Temperature Sensor to stabilize after enabling
C
+7
C
TAERR
Temperature Error
TBD
C
tWAKE
Wakeup Time
80
100
us
General Purpose I/O Port Input Data Sample Timing
Figure 34 illustrates timing of the GPIO Port input sampling. The input value on a GPIO Port pin is sampled on the rising edge of the system clock. The Port value is available to the eZ8 CPU on the second rising clock edge following the change of the Port value.
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TCLK
System Clock Port Value Changes to 0 Port Pin Input Value
Port Input Data Register Latch
0 Latched Into Port Input Data Register Port Input Data Register Value 0 Read by eZ8
Port Input Data Read on Data Bus
Figure 34. Port Input Sample Timing
Table 142. GPIO Port Input Timing
Delay (ns) Parameter Abbreviation Minimum Maximum
TS_PORT TH_PORT TSMR
Port Input Transition to XIN Rise Setup Time (Not pictured) XIN Rise to Port Input Transition Hold Time (Not pictured) GPIO Port Pin Pulse Width to ensure STOP Mode Recovery (for GPIO Port Pins enabled as SMR sources)
5 0 1s
- -
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General Purpose I/O Port Output Timing
Figure 35 and Table 143 provide timing information for GPIO Port pins.
TCLK
XIN T1 Port Output T2
Figure 35. GPIO Port Output Timing Table 143. GPIO Port Output Timing
Delay (ns) Parameter Abbreviation Minimum Maximum
GPIO Port pins
T1 T2
XIN Rise to Port Output Valid Delay XIN Rise to Port Output Hold Time
- 2
15 -
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On-Chip Debugger Timing
Figure 36 and Table 144 provide timing information for the DBG pin. The DBG pin timing specifications assume a 4ns maximum rise and fall time.
TCLK
XIN T1 DBG (Output) Output Data T2
T3 DBG (Input) Input Data
T4
Figure 36. On-Chip Debugger Timing Table 144. On-Chip Debugger Timing
Delay (ns) Parameter DBG Abbreviation Minimum Maximum
T1 T2 T3 T4
XIN Rise to DBG Valid Delay XIN Rise to DBG Output Hold Time DBG to XIN Rise Input Setup Time DBG to XIN Rise Input Hold Time
- 2 5 5
15 - - -
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UART Timing
Figure 37 and Table 145 provide timing information for UART pins for the case where CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit data register has been loaded with data prior to CTS assertion.
CTS (Input) T3 DE (Output) T1
TXD (Output)
bit 7
parity
stop T2 end of stop bit(s)
start
bit 0
bit 1
Figure 37. UART Timing With CTS Table 145. UART Timing With CTS
Delay (ns) Parameter UART Abbreviation Minimum Maximum
T1 T2 T3
CTS Fall to DE output delay
2 * XIN period 5
2 * XIN period + 1 bit time
DE assertion to TXD falling edge (start bit) delay 5 End of Stop Bit(s) to DE deassertion delay
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Figure 38 and Table 146 provide timing information for UART pins for the case where CTS is not used for flow control. DE asserts after the transmit data register has been written. DE remains asserted for multiple characters as long as the transmit data register is written with the next character before the current character has completed.
T2 DE (Output)
TXD (Output)
start
bit0
bit 1
bit 7
parity
stop end of stop bit(s)
T1
Figure 38. UART Timing Without CTS Table 146. UART Timing Without CTS
Delay (ns) Parameter UART Abbreviation Minimum Maximum
T1 T2
DE assertion to TXD falling edge (start bit) delay End of Stop Bit(s) to DE deassertion delay (Tx data register is empty)
1 * XIN period 5
1 bit time
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Packaging
Figure 39 illustrates the 8-pin Plastic Dual Inline Package (PDIP) available for the Z8 Encore! XP(R) 4K Series devices.
8 5
E1
1
4
E
D
B1 Q1 A2
A1
L
C
CONTROLLING DIMENSIONS : MM.
S
B
e
eA
Figure 39.8-Pin Plastic Dual Inline Package (PDIP)
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Figure 40 illustrates the 8-pin Small Outline Integrated Circuit package (SOIC) available for the Z8 Encore! XP(R) 4K Series devices.
Figure 40. 8-Pin Small Outline Integrated Circuit Package (SOIC)
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Figure 41 illustrates the 8-pin Quad Flat No-Lead package (QFN)/MLF-S available for the Z8 Encore! XP 4K Series devices. This package has a footprint identical to that of the 8pin SOIC, but with a lower profile.
Figure 41.8-Pin Quad Flat No-Lead Package (QFN)/ MLF-S
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Figure 42 illustrates the 20-pin Plastic Dual Inline Package (PDIP) available for the Z8 Encore! XP(R) 4K Series devices.
Figure 42.20-Pin Plastic Dual Inline Package (PDIP)
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Figure 43 illustrates the 20-pin Small Outline Integrated Circuit Package (SOIC) available for the Z8 Encore! XP(R) 4K Series devices.
Figure 43.20-Pin Small Outline Integrated Circuit Package (SOIC)
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Figure 44 illustrates the 20-pin Small Shrink Outline Package (SSOP) available for the Z8 Encore! XP(R) 4K Series devices.
Figure 44.20-Pin Small Shrink Outline Package (SSOP)
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Figure 45 illustrates the 28-pin Plastic Dual Inline Package (PDIP) available for the Z8 Encore! XP(R) 4K Series devices.
Figure 45.28-Pin Plastic Dual Inline Package (PDIP)
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Figure 46 illustrates the 28-pin Small Outline Integrated Circuit package (SOIC) available in the Z8 Encore! XP(R) 4K Series devices.
Figure 46.28-Pin Small Outline Integrated Circuit Package (SOIC)
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Figure 47 illustrates the 28-pin Small Shrink Outline Package (SSOP) available for the Z8 Encore! XP(R) 4K Series devices.
D 28 15 C SYMBOL A E H A1 A2 B C 1 14 DETAIL A D E e MIN 1.73 0.05 1.68 0.25 0.09 10.07 5.20 10.20 5.30 0.65 TYP 7.65 0.63 7.80 0.75 7.90 0.95 0.301 0.025 MILLIMETER NOM 1.86 0.13 1.73 MAX 1.99 0.21 1.78 0.38 0.20 10.33 5.38 MIN 0.068 0.002 0.066 0.010 0.004 0.397 0.205 0.006 0.402 0.209 0.0256 TYP 0.307 0.030 0.311 0.037 INCH NOM 0.073 0.005 0.068 MAX 0.078 0.008 0.070 0.015 0.008 0.407 0.212
Q1
H L A2
A1
A
e
B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L
0-8
Figure 47.28-Pin Small Shrink Outline Package (SSOP)
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Ordering Information
16-Bit Timers w/PWM Temperature Sensor 10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 4KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F042APB020SC Z8F042AQB020SC Z8F042ASB020SC Z8F042ASH020SC Z8F042AHH020SC Z8F042APH020SC Z8F042ASJ020SC Z8F042AHJ020SC Z8F042APJ020SC 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 128B 128B 128B 128B 128B 128B 128B 128B 128B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F042APB020EC Z8F042AQB020EC Z8F042ASB020EC Z8F042ASH020EC Z8F042AHH020EC Z8F042APH020EC Z8F042ASJ020EC Z8F042AHJ020EC Z8F042APJ020EC 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 128B 128B 128B 128B 128B 128B 128B 128B 128B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
240
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 4KB Flash Standard Temperature: 0 to 70C Z8F041APB020SC Z8F041AQB020SC Z8F041ASB020SC Z8F041ASH020SC Z8F041AHH020SC Z8F041APH020SC Z8F041ASJ020SC Z8F041AHJ020SC Z8F041APJ020SC 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 128B 128B 128B 128B 128B 128B 128B 128B 128B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 QFN 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F041APB020EC Z8F041AQB020EC Z8F041ASB020EC Z8F041ASH020EC Z8F041AHH020EC Z8F041APH020EC Z8F041ASJ020EC Z8F041AHJ020EC Z8F041APJ020EC 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 128B 128B 128B 128B 128B 128B 128B 128B 128B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 PDIP 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
241
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 2KB Flash, 10-Bit analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F022APB020SC Z8F022AQB020SC Z8F022ASB020SC Z8F022ASH020SC Z8F022AHH020SC Z8F022APH020SC Z8F022ASJ020SC Z8F022AHJ020SC Z8F022APJ020SC 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 512B 512B 512B 512B 512B 512B 512B 512B 512B 64B 64B 64B 64B 64B 64B 64B 64B 64B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F022APB020EC Z8F022AQB020EC Z8F022ASB020EC Z8F022ASH020EC Z8F022AHH020EC Z8F022APH020EC Z8F022ASJ020EC Z8F022AHJ020EC Z8F022APJ020EC 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 512B 512B 512B 512B 512B 512B 512B 512B 512B 64B 64B 64B 64B 64B 64B 64B 64B 64B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
242
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 2KB Flash Standard Temperature: 0 to 70C Z8F021APB020SC Z8F021AQB020SC Z8F021ASB020SC Z8F021ASH020SC Z8F021AHH020SC Z8F021APH020SC Z8F021ASJ020SC Z8F021AHJ020SC Z8F021APJ020SC 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 512B 512B 512B 512B 512B 512B 512B 512B 512B 64B 64B 64B 64B 64B 64B 64B 64B 64B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 QFN 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F021APB020EC Z8F021AQB020EC Z8F021ASB020EC Z8F021ASH020EC Z8F021AHH020EC Z8F021APH020EC Z8F021ASJ020EC Z8F021AHJ020EC Z8F021APJ020EC 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 2KB 512B 512B 512B 512B 512B 512B 512B 512B 512B 64B 64B 64B 64B 64B 64B 64B 64B 64B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 QFN 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
243
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 1KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F012APB020SC Z8F012AQB020SC Z8F012ASB020SC Z8F012ASH020SC Z8F012AHH020SC Z8F012APH020SC Z8F012ASJ020SC Z8F012AHJ020SC Z8F012APJ020SC 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 256B 256B 256B 256B 256B 256B 256B 256B 256B 16B 16B 16B 16B 16B 16B 16B 16B 16B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F012APB020EC Z8F012AQB020EC Z8F012ASB020EC Z8F012ASH020EC Z8F012AHH020EC Z8F012APH020EC Z8F012ASJ020EC Z8F012AHJ020EC Z8F012APJ020EC 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 256B 256B 256B 256B 256B 256B 256B 256B 256B 16B 16B 16B 16B 16B 16B 16B 16B 16B 6 6 6 17 17 17 23 23 23 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 8 8 8 1 1 1 1 1 1 1 1 1 1 PDIP 8-pin package 1 QFN 8-pin package 1 SOIC 8-pin package 1 SOIC 20-pin package 1 SSOP 20-pin package 1 PDIP 20-pin package 1 SOIC 28-pin package 1 SSOP 28-pin package 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
244
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Z8 Encore! XP(R) with 1KB Flash Standard Temperature: 0 to 70C Z8F011APB020SC Z8F011AQB020SC Z8F011ASB020SC Z8F011ASH020SC Z8F011AHH020SC Z8F011APH020SC Z8F011ASJ020SC Z8F011AHJ020SC Z8F011APJ020SC 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 256B 256B 256B 256B 256B 256B 256B 256B 256B 16B 16B 16B 16B 16B 16B 16B 16B 16B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 QFN 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Extended Temperature: -40 to 105C Z8F011APB020EC Z8F011AQB020EC Z8F011ASB020EC Z8F011ASH020EC Z8F011AHH020EC Z8F011APH020EC Z8F011ASJ020EC Z8F011AHJ020EC Z8F011APJ020EC 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 1KB 256B 256B 256B 256B 256B 256B 256B 256B 256B 16B 16B 16B 16B 16B 16B 16B 16B 16B 6 6 6 17 17 17 25 25 25 18 18 18 18 18 18 18 18 18 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 PDIP 8-pin package 0 QFN 8-pin package 0 SOIC 8-pin package 0 SOIC 20-pin package 0 SSOP 20-pin package 0 PDIP 20-pin package 0 SOIC 28-pin package 0 SSOP 28-pin package 0 PDIP 28-pin package
Replace C with G for Lead-Free Packaging Z8F04A28100KIT 20 and 28-Pin Development Kit
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
245
16-Bit Timers w/PWM
Temperature Sensor
10-Bit A/D Channels
UART with IrDA
Part Number
Comparator
Z8F04A08100KIT ZUSBSC0100ZAC
8-Pin Development Kit USB Smart Cable Accessory Kit
PS022815-0206
Description
Ordering Information
Interrupts
I/O Lines
NVDS
Flash
RAM
Z8 Encore! XP(R) 4K Series Product Specification
246
Part Number Suffix Designations
Z8 F 04 2A S H 020 S C Environmental Flow: C = Standard Plastic Packaging Compound G = Green Plastic Packaging Compound Temperature Range (C): S = Standard, 0 to 70 E = Extended, -40 to +105 Speed: 020 = 20MHz Pin Count: B=8 H = 20 J = 28 Package: H = SSOP P = PDIP Q = QFN S = SOIC Device Type Memory Size: 04 = 4KB Flash, 1KB RAM, 128B NVDS 02 = 2KB Flash, 512B RAM, 64B NVDS 01 = 1KB Flash, 256B RAM, 32B NVDS Memory Type: F = Flash Device Family
PS022815-0206
Ordering Information
Z8 Encore! XP(R) 4K Series Product Specification
247
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, because of start-up yield issues.
ZiLOG, Inc. 532 Race Street San Jose, CA 95126 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com
Customer Support
For valuable information about downloading other relevant documents or for hardware and software development tools, visit the ZiLOG web site at www.zilog.com.
PS022815-0206
Ordering Information
Z8 Encore! XP(R) 4K Series Product Specification
248
Customer Feedback Form
Customer Support
If you experience any problems while operating this product, please check the ZiLOG Knowledge Base: http://kb.zilog.com/kb/oKBmain.asp If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page: http://support.zilog.com
PS022815-0206
Customer Feedback Form
Z8 Encore! XP(R) 4K Series Product Specification
249
Index
Symbols
# 194 % 194 @ 194
ANDX 197 arithmetic instructions 195 assembly language programming 191 assembly language syntax 192
B
B 194 b 193 baud rate generator, UART 99 BCLR 196 binary number suffix 194 BIT 196 bit 193 clear 196 manipulation instructions 196 set 196 set or clear 196 swap 196 test and jump 198 test and jump if non-zero 198 test and jump if zero 198 bit jump and test if non-zero 198 bit swap 198 block diagram 2 block transfer instructions 196 BRK 198 BSET 196 BSWAP 196, 198 BTJ 198 BTJNZ 198 BTJZ 198
Numerics
10-bit ADC 4 40-lead plastic dual-inline package 237, 238
A
absolute maximum ratings 212 AC characteristics 217 ADC 195 architecture 113 automatic power-down 114 block diagram 114 continuous conversion 116 control register 124, 126 control register definitions 124 data high byte register 127 data low bits register 127 electrical characteristics and timing 221 operation 114 single-shot conversion 115 ADCCTL register 124, 126 ADCDH register 127 ADCDL register 127 ADCX 195 ADD 195 add - extended addressing 195 add with carry 195 add with carry - extended addressing 195 additional symbols 194 address space 13 ADDX 195 analog signals 10 analog-to-digital converter (ADC) 113 AND 197
PS022815-0206
C
CALL procedure 198 capture mode 80, 81 capture/compare mode 80 cc 193 CCF 196 characteristics, electrical 212 clear 197 CLR 197 COM 197
Index
Z8 Encore! XP(R) 4K Series Product Specification
250
compare 80 compare - extended addressing 195 compare mode 80 compare with carry 195 compare with carry - extended addressing 195 complement 197 complement carry flag 196 condition code 193 continuous conversion (ADC) 116 continuous mode 80 control register definition, UART 100 Control Registers 13, 16 counter modes 80 CP 195 CPC 195 CPCX 195 CPU and peripheral overview 4 CPU control instructions 196 CPX 195 Customer Feedback Form 248 Customer Information 248
E
EI 196 electrical characteristics 212 ADC 221 flash memory and timing 220 GPIO input data sample timing 224 watch-dog timer 220, 223 enable interrupt 196 ER 193 extended addressing register 193 external pin reset 24 eZ8 CPU features 4 eZ8 CPU instruction classes 194 eZ8 CPU instruction notation 192 eZ8 CPU instruction set 191 eZ8 CPU instruction summary 199
F
FCTL register 144, 150, 151 features, Z8 Encore! 1 first opcode map 210 FLAGS 194 flags register 194 flash controller 4 option bit address space 151 option bit configuration - reset 148 program memory address 0000H 151 program memory address 0001H 152 flash memory 136 arrrangement 137 byte programming 142 code protection 140 configurations 136 control register definitions 144, 150 controller bypass 143 electrical characteristics and timing 220 flash control register 144, 150, 151 flash option bits 141 flash status register 145 flow chart 139 frequency high and low byte registers 147 mass erase 142
Index
D
DA 193, 195 data memory 15 DC characteristics 213 debugger, on-chip 167 DEC 195 decimal adjust 195 decrement 195 decrement and jump non-zero 198 decrement word 195 DECW 195 destination operand 194 device, port availability 32 DI 196 direct address 193 disable interrupts 196 DJNZ 198 dst 194
PS022815-0206
Z8 Encore! XP(R) 4K Series Product Specification
251
operation 138 operation timing 140 page erase 142 page select register 145, 146 FPS register 145, 146 FSTAT register 145
G
gated mode 80 general-purpose I/O 32 GPIO 4, 32 alternate functions 33 architecture 33 control register definitions 40 input data sample timing 224 interrupts 40 port A-C pull-up enable sub-registers 45, 46 port A-H address registers 41 port A-H alternate function sub-registers 42 port A-H control registers 42 port A-H data direction sub-registers 42 port A-H high drive enable sub-registers 44 port A-H input data registers 46 port A-H output control sub-registers 43 port A-H output data registers 47 port A-H stop mode recovery sub-registers 44 port availability by device 32 port input timing 225 port output timing 226
H
H 194 HALT 196 halt mode 30, 196 hexadecimal number prefix/suffix 194
I
I2C 4 IM 193
PS022815-0206
immediate data 193 immediate operand prefix 194 INC 195 increment 195 increment word 195 INCW 195 indexed 193 indirect address prefix 194 indirect register 193 indirect register pair 193 indirect working register 193 indirect working register pair 193 infrared encoder/decoder (IrDA) 109 Instruction Set 191 instruction set, ez8 CPU 191 instructions ADC 195 ADCX 195 ADD 195 ADDX 195 AND 197 ANDX 197 arithmetic 195 BCLR 196 BIT 196 bit manipulation 196 block transfer 196 BRK 198 BSET 196 BSWAP 196, 198 BTJ 198 BTJNZ 198 BTJZ 198 CALL 198 CCF 196 CLR 197 COM 197 CP 195 CPC 195 CPCX 195 CPU control 196 CPX 195 DA 195 DEC 195
Index
Z8 Encore! XP(R) 4K Series Product Specification
252
DECW 195 DI 196 DJNZ 198 EI 196 HALT 196 INC 195 INCW 195 IRET 198 JP 198 LD 197 LDC 197 LDCI 196, 197 LDE 197 LDEI 196 LDX 197 LEA 197 load 197 logical 197 MULT 195 NOP 196 OR 197 ORX 197 POP 197 POPX 197 program control 198 PUSH 197 PUSHX 197 RCF 196 RET 198 RL 198 RLC 198 rotate and shift 198 RR 198 RRC 198 SBC 195 SCF 196 SRA 198 SRL 199 SRP 196 STOP 197 SUB 195 SUBX 195 SWAP 199 TCM 196
TCMX 196 TM 196 TMX 196 TRAP 198 watch-dog timer refresh 197 XOR 198 XORX 198 instructions, eZ8 classes of 194 interrupt control register 61 interrupt controller 50 architecture 50 interrupt assertion types 53 interrupt vectors and priority 53 operation 52 register definitions 54 software interrupt assertion 54 interrupt edge select register 60 interrupt request 0 register 54 interrupt request 1 register 55 interrupt request 2 register 56 interrupt return 198 interrupt vector listing 50 interrupts UART 97 IR 193 Ir 193 IrDA architecture 109 block diagram 109 control register definitions 112 operation 109 receiving data 111 transmitting data 110 IRET 198 IRQ0 enable high and low bit registers 57 IRQ1 enable high and low bit registers 58 IRQ2 enable high and low bit registers 59 IRR 193 Irr 193
J
JP 198 jump, conditional, relative, and relative condi-
PS022815-0206
Index
Z8 Encore! XP(R) 4K Series Product Specification
253
tional 198
L
LD 197 LDC 197 LDCI 196, 197 LDE 197 LDEI 196, 197 LDX 197 LEA 197 load 197 load constant 196 load constant to/from program memory 197 load constant with auto-increment addresses 197 load effective address 197 load external data 197 load external data to/from data memory and auto-increment addresses 196 load external to/from data memory and auto-increment addresses 197 load instructions 197 load using extended addressing 197 logical AND 197 logical AND/extended addressing 197 logical exclusive OR 198 logical exclusive OR/extended addressing 198 logical instructions 197 logical OR 197 logical OR/extended addressing 197 low power modes 29
gated 80 one-shot 79 PWM 80 modes 80 MULT 195 multiply 195 multiprocessor mode, UART 95
N
NOP (no operation) 196 notation b 193 cc 193 DA 193 ER 193 IM 193 IR 193 Ir 193 IRR 193 Irr 193 p 193 R 193 r 193 RA 193 RR 193 rr 193 vector 193 X 193 notational shorthand 193
O
OCD architecture 167 auto-baud detector/generator 170 baud rate limits 170 block diagram 167 breakpoints 172 commands 172 control register 177 data format 170 DBG pin to RS-232 Interface 168 debug mode 169
M
master interrupt enable 52 memory data 15 program 14 mode capture 80, 81 capture/compare 80 continuous 80 counter 80
PS022815-0206
Index
Z8 Encore! XP(R) 4K Series Product Specification
254
debugger break 198 interface 168 serial errors 171 status register 178 timing 227 OCD commands execute instruction (12H) 177 read data memory (0DH) 176 read OCD control register (05H) 174 read OCD revision (00H) 174 read OCD status register (02H) 174 read program counter (07H) 175 read program memory (0BH) 175 read program memory CRC (0EH) 176 read register (09H) 175 read runtime counter (03H) 174 step instruction (10H) 177 stuff instruction (11H) 177 write data memory (0CH) 176 write OCD control register (04H) 174 write program counter (06H) 174 write program memory (0AH) 175 write register (08H) 175 on-chip debugger (OCD) 167 on-chip debugger signals 10 on-chip oscillator 185 one-shot mode 79 opcode map abbreviations 209 cell description 208 first 210 second after 1FH 211 Operational Description 20, 29, 32, 50, 62, 83, 89, 109, 113, 130, 134, 136, 148, 163, 167, 180, 185, 190 OR 197 ordering information 239 ORX 197 oscillator signals 10
20-pin PDIP 233, 234 20-pin SSOP 235, 238 28-pin PDIP 236 28-pin SOIC 237 8-pin PDIP 230 8-pin SOIC 231 PDIP 237, 238 part selection guide 2 PC 194 PDIP 237, 238 peripheral AC and DC electrical characteristics 219 pin characteristics 11 Pin Descriptions 7 polarity 193 POP 197 pop using extended addressing 197 POPX 197 port availability, device 32 port input timing (GPIO) 225 port output timing, GPIO 226 power supply signals 10 power-down, automatic (ADC) 114 power-on and voltage brown-out electrical characteristics and timing 219 power-on reset (POR) 22 program control instructions 198 program counter 194 program memory 14 PUSH 197 push using extended addressing 197 PUSHX 197 PWM mode 80 PxADDR register 41 PxCTL register 42
R
R 193 r 193 RA register address 193 RCF 196 receive
P
p 193 packaging
PS022815-0206
Index
Z8 Encore! XP(R) 4K Series Product Specification
255
IrDA data 111 receiving UART data-interrupt-driven method 94 receiving UART data-polled method 93 register 193 ADC control (ADCCTL) 124, 126 ADC data high byte (ADCDH) 127 ADC data low bits (ADCDL) 127 flash control (FCTL) 144, 150, 151 flash high and low byte (FFREQH and FREEQL) 147 flash page select (FPS) 145, 146 flash status (FSTAT) 145 GPIO port A-H address (PxADDR) 41 GPIO port A-H alternate function sub-registers 43 GPIO port A-H control address (PxCTL) 42 GPIO port A-H data direction sub-registers 42 OCD control 177 OCD status 178 UARTx baud rate high byte (UxBRH) 106 UARTx baud rate low byte (UxBRL) 106 UARTx Control 0 (UxCTL0) 103, 106 UARTx control 1 (UxCTL1) 104 UARTx receive data (UxRXD) 101 UARTx status 0 (UxSTAT0) 101 UARTx status 1 (UxSTAT1) 103 UARTx transmit data (UxTXD) 100 watch-dog timer control (WDTCTL) 28, 86, 131, 183 watch-dog timer reload high byte (WDTH) 87 watch-dog timer reload low byte (WDTL) 88 watch-dog timer reload upper byte (WDTU) 87 register file 13 register pair 193 register pointer 194 reset and stop mode characteristics 21 and stop mode recovery 20 carry flag 196
sources 22 RET 198 return 198 RL 198 RLC 198 rotate and shift instuctions 198 rotate left 198 rotate left through carry 198 rotate right 198 rotate right through carry 198 RP 194 RR 193, 198 rr 193 RRC 198
S
SBC 195 SCF 196 second opcode map after 1FH 211 set carry flag 196 set register pointer 196 shift right arithmatic 198 shift right logical 199 signal descriptions 9 single-sho conversion (ADC) 115 software trap 198 source operand 194 SP 194 SRA 198 src 194 SRL 199 SRP 196 stack pointer 194 STOP 197 stop mode 29, 197 stop mode recovery sources 25, 27 using a GPIO port pin transition 26, 27 using watch-dog timer time-out 26 SUB 195 subtract 195 subtract - extended addressing 195 subtract with carry 195
PS022815-0206
Index
Z8 Encore! XP(R) 4K Series Product Specification
256
subtract with carry - extended addressing 195 SUBX 195 SWAP 199 swap nibbles 199 symbols, additional 194
TRAP 198
U
UART 4 architecture 89 baud rate generator 99 baud rates table 107 control register definitions 100 controller signals 9 data format 90 interrupts 97 multiprocessor mode 95 receiving data using interrupt-driven method 94 receiving data using the polled method 93 transmitting data usin the interrupt-driven method 92 transmitting data using the polled method 91 x baud rate high and low registers 106 x control 0 and control 1 registers 103 x status 0 and status 1 registers 101, 103 UxBRH register 106 UxBRL register 106 UxCTL0 register 103, 106 UxCTL1 register 104 UxRXD register 101 UxSTAT0 register 101 UxSTAT1 register 103 UxTXD register 100
T
TCM 196 TCMX 196 test complement under mask 196 test complement under mask - extended addressing 196 test under mask 196 test under mask - extended addressing 196 timer signals 9 timers 62 architecture 62 block diagram 63 capture mode 70, 71, 80, 81 capture/compare mode 74, 80 compare mode 72, 80 continuous mode 64, 80 counter mode 65, 66 counter modes 80 gated mode 73, 80 one-shot mode 63, 79 operating mode 63 PWM mode 67, 69, 80 reading the timer count values 75 reload high and low byte registers 76 timer control register definitions 76 timer output signal operation 75 timers 0-3 control registers 78, 79 high and low byte registers 76, 77 TM 196 TMX 196 tools, hardware and software 247 transmit IrDA data 110 transmitting UART data-polled method 91 transmitting UART dat-interrupt-driven method 92
V
vector 193 voltage brown-out reset (VBR) 23
W
watch-dog timer approximate time-out delay 84 approximate time-out delays 83, 130, 134, 163, 180, 190 CNTL 23
Index
PS022815-0206
Z8 Encore! XP(R) 4K Series Product Specification
257
control register 86, 131, 183 electrical characteristics and timing 220, 223 interrupt in noromal operation 84 interrupt in stop mode 85 operation 83, 130, 134, 163, 180, 190 refresh 84, 197 reload unlock sequence 85 reload upper, high and low registers 87 reset 24 reset in normal operation 85 reset in Stop mode 85 time-out response 84 WDTCTL register 28, 86, 131, 183 WDTH register 87 WDTL register 88 working register 193 working register pair 193 WTDU register 87
X
X 193 XOR 198 XORX 198
Z
Z8 Encore! block diagram 2 features 1 part selection guide 2
PS022815-0206
Index

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